ENC28J60
The Ethernet buffer contains transmit and receive
memory used by the Ethernet controller in a single
memory space. The sizes of the memory areas are
programmable by the host controller using the SPI
interface. The Ethernet buffer memory can only be
accessed via the read buffer memory and write buffer
memory SPI commands (see Section 4.2.2 “Read
Buffer Memory Command” and Section 4.2.4 “Write
Buffer Memory Command”).
3.0
MEMORY ORGANIZATION
All memory in the ENC28J60 is implemented as static
RAM. There are three types of memory in the
ENC28J60:
• Control Registers
• Ethernet Buffer
• PHY Registers
The Control registers’ memory contains the registers
that are used for configuration, control and status
retrieval of the ENC28J60. The Control registers are
directly read and written to by the SPI interface.
The PHY registers are used for configuration, control
and status retrieval of the PHY module. The registers
are not directly accessible through the SPI interface;
they can only be accessed through Media Independent
Interface Management (MIIM) implemented in the
MAC.
Figure 3-1 shows the data memory organization for the
ENC28J60.
FIGURE 3-1:
ENC28J60 MEMORY ORGANIZATION
ECON1<1:0>
Control Registers
Ethernet Buffer
00h
0000h
Buffer Pointers in Bank 0
= 00
= 01
= 10
Bank 0
Bank 1
Bank 2
19h
1Ah
Common
Registers
1Fh
00h
19h
1Ah
Common
Registers
1Fh
00h
19h
1Ah
Common
Registers
1FFFh
1Fh
00h
= 11
PHY Registers
Bank 3
19h
1Ah
00h
Common
Registers
1Fh
1Fh
Note:
Memory areas are not shown to scale. The size of the control memory space has been scaled to show detail.
© 2006 Microchip Technology Inc.
Preliminary
DS39662B-page 11
MICROCHIP [ MICROCHIP ]
