ENC28J60
3.1.2
ECON2 REGISTER
The ECON2 register, shown in Register 3-2, is used to
control other main functions of the ENC28J60.
REGISTER 3-2:
ECON2: ETHERNET CONTROL REGISTER 2
R/W-1
R/W-0(1)
PKTDEC
R/W-0
R/W-0
r
R/W-0
VRPS
U-0
—
U-0
—
U-0
—
AUTOINC
bit 7
PWRSV
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
AUTOINC: Automatic Buffer Pointer Increment Enable bit
1= Automatically increment ERDPT or EWRPT on reading from or writing to EDATA
0= Do not automatically change ERDPT and EWRPT after the buffer is accessed
PKTDEC: Packet Decrement bit
1= Decrement the EPKTCNT register by one
0= Leave EPKTCNT unchanged
PWRSV: Power Save Enable bit
1= MAC, PHY and control logic are in Low-Power Sleep mode
0= Normal operation
bit 4
bit 3
Reserved: Maintain as ‘0’
VRPS: Voltage Regulator Power Save Enable bit
When PWRSV = 1:
1= Internal voltage regulator is in Low-Current mode
0= Internal voltage regulator is in Normal Current mode
When PWRSV = 0:
The bit is ignored; the regulator always outputs as much current as the device requires.
bit 2-0
Unimplemented: Read as ‘0’
Note 1: This bit is automatically cleared once it is set.
DS39662B-page 16
Preliminary
© 2006 Microchip Technology Inc.
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