ENC28J60
Stand-Alone Ethernet Controller with SPI Interface
Ethernet Controller Features
• IEEE 802.3 compatible Ethernet controller
• Integrated MAC and 10BASE-T PHY
• Supports one 10BASE-T port with automatic
polarity detection and correction
• Supports Full and Half-Duplex modes
• Programmable automatic retransmit on collision
• Programmable padding and CRC generation
• Programmable automatic rejection of erroneous
packets
• SPI Interface with clock speeds up to 20 MHz
Operational
Six interrupt sources and one interrupt output pin
25 MHz clock input requirement
Clock out pin with programmable prescaler
Operating voltage of 3.1V to 3.6V (3.3V typical)
5V tolerant inputs
Temperature range: -40°C to +85°C Industrial,
0°C to +70°C Commercial (SSOP only)
• 28-pin SPDIP, SSOP, SOIC, QFN packages
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•
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•
•
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Package Types
28-Pin SPDIP, SSOP, SOIC
V
CAP
V
SS
CLKOUT
INT
NC*
SO
SI
SCK
CS
RESET
V
SSRX
TPIN-
TPIN+
RBIAS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
LEDA
LEDB
V
DDOSC
OSC2
OSC1
V
SSOSC
V
SSPLL
V
DDPLL
V
DDRX
V
SSTX
TPOUT+
TPOUT-
V
DDTX
Buffer
8-Kbyte transmit/receive packet dual port SRAM
Configurable transmit/receive buffer size
Hardware-managed circular receive FIFO
Byte-wide random and sequential access with
auto-increment
• Internal DMA for fast data movement
• Hardware assisted checksum calculation for vari-
ous network protocols
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•
ENC28J60
Medium Access Controller (MAC)
Features
• Supports Unicast, Multicast and Broadcast
packets
• Programmable receive packet filtering and
wake-up host on logical AND or OR of the
following:
- Unicast destination address
- Multicast address
- Broadcast address
- Magic Packet™
- Group destination addresses as defined by
64-bit hash table
- Programmable pattern matching of up to
64 bytes at user-defined offset
28-pin QFN
28 27 26 25 24 23 22
NC*
SO
SI
SCK
CS
RESET
V
SSRX
1
2
3
4
5
6
7
21
20
19
18
17
16
15
V
DDOSC
OSC2
OSC1
V
SSOSC
V
SSPLL
V
DDPLL
V
DDRX
Physical Layer (PHY) Features
TPIN-
TPIN+
RBIAS
V
DDTX
• Loopback mode
• Two programmable LED outputs for LINK, TX,
RX, collision and full/half-duplex status
* Reserved pin; always leave disconnected.
©
2006 Microchip Technology Inc.
Preliminary
TPOUT-
TPOUT+
V
SSTX
INT
CLKOUT
V
SS
V
CAP
V
DD
LEDA
LEDB
ENC28J60
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DS39662B-page 1
MICROCHIP [ MICROCHIP TECHNOLOGY ]
