ENC28J60
Stand-Alone Ethernet Controller with SPI Interface
Ethernet Controller Features
Operational
• IEEE 802.3 compatible Ethernet controller
• Integrated MAC and 10BASE-T PHY
• Six interrupt sources and one interrupt output pin
• 25 MHz clock input requirement
• Supports one 10BASE-T port with automatic
polarity detection and correction
• Clock out pin with programmable prescaler
• Operating voltage of 3.1V to 3.6V (3.3V typical)
• 5V tolerant inputs
• Supports Full and Half-Duplex modes
• Programmable automatic retransmit on collision
• Programmable padding and CRC generation
• Temperature range: -40°C to +85°C Industrial,
0°C to +70°C Commercial (SSOP only)
• Programmable automatic rejection of erroneous
packets
• 28-pin SPDIP, SSOP, SOIC, QFN packages
• SPI Interface with clock speeds up to 20 MHz
Package Types
28-Pin SPDIP, SSOP, SOIC
Buffer
VDD
28
27
26
25
1
2
3
4
5
6
7
8
9
10
VCAP
VSS
CLKOUT
INT
• 8-Kbyte transmit/receive packet dual port SRAM
• Configurable transmit/receive buffer size
• Hardware-managed circular receive FIFO
LEDA
LEDB
VDDOSC
OSC2
OSC1
VSSOSC
VSSPLL
VDDPLL
VDDRX
VSSTX
24
23
22
21
20
19
18
17
16
15
NC*
SO
SI
SCK
CS
RESET
VSSRX
TPIN-
TPIN+
RBIAS
• Byte-wide random and sequential access with
auto-increment
• Internal DMA for fast data movement
• Hardware assisted checksum calculation for vari-
ous network protocols
11
12
13
14
TPOUT+
TPOUT-
VDDTX
Medium Access Controller (MAC)
Features
• Supports Unicast, Multicast and Broadcast
packets
28-pin QFN
• Programmable receive packet filtering and
wake-up host on logical AND or OR of the
following:
- Unicast destination address
- Multicast address
28 27 26 25 24 23 22
VDDOSC
1
21
20
19
18
17
16
NC*
SO
SI
SCK
CS
- Broadcast address
- Magic Packet™
OSC2
OSC1
2
3
4
5
6
7
ENC28J60
VSSOSC
VSSPLL
VDDPLL
VDDRX
- Group destination addresses as defined by
64-bit hash table
RESET
VSSRX
15
- Programmable pattern matching of up to
64 bytes at user-defined offset
8
9 10 11 12 13 14
Physical Layer (PHY) Features
• Loopback mode
• Two programmable LED outputs for LINK, TX,
RX, collision and full/half-duplex status
* Reserved pin; always leave disconnected.
© 2006 Microchip Technology Inc.
Preliminary
DS39662B-page 1
MICROCHIP [ MICROCHIP ]
