ATmega48/88/168
12.8 8-bit Timer/Counter Register Description
12.8.1
Timer/Counter Control Register A – TCCR0A
Bit
7
COM0A1
R/W
6
COM0A0
R/W
5
COM0B1
R/W
4
COM0B0
R/W
3
–
2
–
1
WGM01
R/W
0
0
WGM00
R/W
0
TCCR0A
Read/Write
Initial Value
R
0
R
0
0
0
0
0
• Bits 7:6 – COM0A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting. Table 12-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits
are set to a normal or CTC mode (non-PWM).
Table 12-2. Compare Output Mode, non-PWM Mode
COM0A1
COM0A0
Description
0
0
1
1
0
1
0
1
Normal port operation, OC0A disconnected.
Toggle OC0A on Compare Match
Clear OC0A on Compare Match
Set OC0A on Compare Match
Table 12-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Table 12-3. Compare Output Mode, Fast PWM Mode(1)
COM0A1
COM0A0
Description
0
0
Normal port operation, OC0A disconnected.
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
0
1
1
1
0
1
Clear OC0A on Compare Match, set OC0A at TOP
Set OC0A on Compare Match, clear OC0A at TOP
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See ”Fast PWM Mode” on page 94
for more details.
99
2545E–AVR–02/05
MICROCHIP [ MICROCHIP ]
