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ATMEGA48V-10MUR 参数 Datasheet PDF下载

ATMEGA48V-10MUR图片预览
型号: ATMEGA48V-10MUR
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 4KB FLASH 32VQFN]
分类和应用: 时钟微控制器外围集成电路闪存
文件页数/大小: 359 页 / 2546 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第96页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第97页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第98页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第99页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第101页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第102页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第103页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第104页  
Table 12-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor-  
rect PWM mode.  
Table 12-4. Compare Output Mode, Phase Correct PWM Mode(1)  
COM0A1  
COM0A0  
Description  
0
0
Normal port operation, OC0A disconnected.  
WGM02 = 0: Normal Port Operation, OC0A Disconnected.  
WGM02 = 1: Toggle OC0A on Compare Match.  
0
1
1
1
0
1
Clear OC0A on Compare Match when up-counting. Set OC0A on  
Compare Match when down-counting.  
Set OC0A on Compare Match when up-counting. Clear OC0A on  
Compare Match when down-counting.  
Note:  
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-  
pare Match is ignored, but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on  
page 121 for more details.  
• Bits 5:4 – COM0B1:0: Compare Match Output B Mode  
These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0  
bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected  
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin  
must be set in order to enable the output driver.  
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the  
WGM02:0 bit setting. Table 12-5 shows the COM0B1:0 bit functionality when the WGM02:0 bits  
are set to a normal or CTC mode (non-PWM).  
Table 12-5. Compare Output Mode, non-PWM Mode  
COM0B1  
COM0B0  
Description  
0
0
1
1
0
1
0
1
Normal port operation, OC0B disconnected.  
Toggle OC0B on Compare Match  
Clear OC0B on Compare Match  
Set OC0B on Compare Match  
Table 12-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM  
mode.  
Table 12-6. Compare Output Mode, Fast PWM Mode(1)  
COM0B1  
COM0B0  
Description  
0
0
1
1
0
1
0
1
Normal port operation, OC0B disconnected.  
Reserved  
Clear OC0B on Compare Match, set OC0B at TOP  
Set OC0B on Compare Match, clear OC0B at TOP  
Note:  
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-  
pare Match is ignored, but the set or clear is done at TOP. See ”Fast PWM Mode” on page 94  
for more details.  
100  
ATmega48/88/168  
2545E–AVR–02/05  
 
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