7.4
Watchdog Timer
ATmega16/32/64/M1/C1 has an enhanced watchdog timer (WDT). The main features are:
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Clocked from separate on-chip oscillator
3 operating modes
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Interrupt
System reset
Interrupt and system reset
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Selectable time-out period from 16ms to 8s
Possible hardware fuse watchdog always on (WDTON) for fail-safe mode
Figure 7-7. Watchdog Timer
128kHz
Watchdog
Prescaler
Oscillator
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDP3
WDE
MCU RESET
INTERRUPT
WDIF
WDIE
The watchdog timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or
a system reset when the counter reaches a given time-out value. In normal operation mode, it is required that the system
uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached. If the system
doesn't restart the counter, an interrupt or system reset will be issued.
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from
sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations,
giving an interrupt when the operation has run longer than expected. In system reset mode, the WDT gives a reset when the
timer expires. This is typically used to prevent system hang-up in case of runaway code. The third mode, interrupt and
system reset mode, combines the other two modes by first giving an interrupt and then switch to system reset mode. This
mode will for instance allow a safe shutdown by saving critical parameters before a system reset.
The “Watchdog Timer Always On” (WDTON) fuse, if programmed, will force the watchdog timer to system reset mode. With
the fuse programmed the system reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To
further ensure program security, alterations to the watchdog set-up must follow timed sequences. The sequence for clearing
WDE and changing time-out configuration is as follows:
1. In the same operation, write a logic one to the watchdog change enable bit (WDCE) and WDE. A logic one must
be written to WDE regardless of the previous value of the WDE bit.
2. Within the next four clock cycles, write the WDE and watchdog prescaler bits (WDP) as desired, but with the
WDCE bit cleared. This must be done in one operation.
ATmega16/32/64/M1/C1 [DATASHEET]
43
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
