Table 7-1.
Parameter
Reset Characteristics
Symbol
V
POT
V
PORMAX
V
PORMIN
V
CCRR
V
RST
t
RST
–0.1
0.01
0.1 V
CC
2.5
-
0.9V
CC
-
Min
1.1
0.8
Typ
1.4
0.9
Max
1.7
1.6
0.4
Unit
V
V
V
V
V/ms
V
µs
Power-on reset threshold voltage (rising)
Power-on reset threshold voltage (falling)
(1)
VCC max. start voltage to ensure internal power-on reset
signal
VCC min. start voltage to ensure internal power-on reset
signal
VCC rise rate to ensure power-on reset
RESET pin threshold voltage
Minimum pulse width on RESET pin
Note:
1.
Before rising, the supply has to be between
V
PORMIN
and V
PORMAX
to ensure a reset.
7.2.1
Power-on Reset
A power-on reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in
Table 7-1.
The
POR is activated whenever V
CC
is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
well as to detect a failure in supply voltage.
A power-on reset (POR) circuit ensures that the device is reset from power-on. Reaching the power-on reset threshold
voltage invokes the delay counter, which determines how long the device is kept in RESET after V
CC
rise. The RESET signal
is activated again, without any delay, when V
CC
decreases below the detection level.
Figure 7-2. MCU Start-up, RESET Tied to V
CC
V
CCRR
V
CC
V
PORMAX
V
PORMIN
RESET
V
RST
t
TOUT
TIME-OUT
INTERNAL
RESET
Figure 7-3. MCU Start-up, RESET Extended Externally
V
CC
V
POT
RESET
V
RST
t
TOUT
TIME-OUT
INTERNAL
RESET
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
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