If WDE is set, the watchdog timer is in interrupt and system reset mode. The first time-out in the watchdog timer will set
WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the watchdog
goes to system reset mode). This is useful for keeping the watchdog timer security while using the interrupt. To stay in
interrupt and system reset mode, WDIE must be set after each interrupt.This should however not be done within the interrupt
service routine itself, as this might compromise the safety-function of the watchdog system reset mode. If the interrupt is not
executed before the next time-out, a system reset will be applied.
Table 7-5. Watchdog Timer Configuration
WDTON(1)
WDE
WDIE
Mode
Action on Time-out
None
1
1
1
0
0
1
0
1
0
Stopped
Interrupt mode
System reset mode
Interrupt
Reset
Interrupt, then go to system reset
mode
1
0
1
x
1
x
Interrupt and system reset mode
System reset mode
Reset
Note:
1. For the WDTON fuse “1” means unprogrammed while “0” means programmed.
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler
bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF
must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the
failure.
• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the watchdog timer prescaling when the watchdog timer is running. The different prescaling
values and their corresponding time-out periods are shown in Table 7-6 on page 46.
Table 7-6. Watchdog Timer Prescale Select
Typical Time-out at
WDP3
WDP2
WDP1
WDP0
Number of WDT Oscillator Cycles
2K (2048) cycles
VCC = 5.0V
16ms
32ms
64ms
0.125s
0.25s
0.5s
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4K (4096) cycles
8K (8192) cycles
16K (16384) cycles
32K (32768) cycles
64K (65536) cycles
128K (131072) cycles
256K (262144) cycles
512K (524288) cycles
1024K (1048576) cycles
1.0s
2.0s
4.0s
8.0s
Reserved
46
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
