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ATMEGA16M1-15MZ 参数 Datasheet PDF下载

ATMEGA16M1-15MZ图片预览
型号: ATMEGA16M1-15MZ
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 16KB FLASH 32QFN]
分类和应用: 微控制器
文件页数/大小: 318 页 / 7595 K
品牌: MICROCHIP [ MICROCHIP ]
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The following code example shows one assembly and one C function for changing the time-out value of the watchdog timer.  
Assembly Code Example(1)  
WDT_Prescaler_Change:  
; Turn off global interrupt  
cli  
; Reset Watchdog Timer  
wdr  
; Start timed sequence  
lds r16, WDTCSR  
ori  
r16, (1<<WDCE) | (1<<WDE)  
sts WDTCSR, r16  
; -- Got four cycles to set the new values from here -  
; Set new prescaler(time-out) value = 64K cycles (~0.5 s)  
ldi  
r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)  
sts WDTCSR, r16  
; -- Finished setting new values, used 2 cycles -  
; Turn on global interrupt  
sei  
ret  
C Code Example(1)  
void WDT_Prescaler_Change(void)  
{
__disable_interrupt();  
__watchdog_reset();  
/* Start timed sequence */  
WDTCSR |= (1<<WDCE) | (1<<WDE);  
/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */  
WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);  
__enable_interrupt();  
}
Notes: 1. The example code assumes that the part specific header file is included.  
2. The watchdog timer should be reset before any change of the WDP bits, since a change in the WDP bits can  
result in a time-out when switching to a shorter time-out period;  
7.4.1 Watchdog Timer Control Register - WDTCSR  
Bit  
7
WDIF  
R/W  
0
6
WDIE  
R/W  
0
5
WDP3  
R/W  
0
4
WDCE  
R/W  
0
3
2
WDP2  
R/W  
0
1
WDP1  
R/W  
0
0
WDP0  
R/W  
0
WDE  
R/W  
X
WDTCSR  
Read/Write  
Initial Value  
• Bit 7 - WDIF: Watchdog Interrupt Flag  
This bit is set when a time-out occurs in the watchdog timer and the watchdog timer is configured for interrupt. WDIF is  
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a  
logic one to the flag. When the I-bit in SREG and WDIE are set, the watchdog time-out interrupt is executed.  
• Bit 6 - WDIE: Watchdog Interrupt Enable  
When this bit is written to one and the I-bit in the status register is set, the watchdog interrupt is enabled. If WDE is cleared in  
combination with this setting, the watchdog timer is in interrupt mode, and the corresponding interrupt is executed if time-out  
in the watchdog timer occurs.  
ATmega16/32/64/M1/C1 [DATASHEET]  
45  
7647O–AVR–01/15  
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