• Bit 6:5 – SJW1:0: Re-Synchronization Jump Width
To compensate for phase shifts between clock oscillators of different bus controllers, the controller must re-synchronize on
any relevant signal edge of the current transmission. The synchronization jump width defines the maximum number of clock
cycles. A bit period may be shortened or lengthened by a re-synchronization.
Tsjw = Tscl SJW[1:0] + 1
• Bit 4 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT2 is written.
• Bit 3:1 – PRS2:0: Propagation Time Segment
This part of the bit time is used to compensate for the physical delay times within the network. It is twice the sum of the signal
propagation time on the bus line, the input comparator delay and the output driver delay.
Tprs = Tscl PRS[2:0] + 1
• Bit 0 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT2 is written.
16.10.10 CAN Bit Timing Register 3 - CANBT3
Bit
7
-
6
PHS22
R/W
0
5
PHS21
R/W
0
4
PHS20
R/W
0
3
PHS12
R/W
0
2
PHS11
R/W
0
1
PHS10
R/W
0
0
SMP
R/W
0
CANBT3
Read/Write
Initial Value
-
-
• Bit 7– Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT3 is written.
• Bit 6:4 – PHS22:0: Phase Segment 2
This phase is used to compensate for phase edge errors. This segment may be shortened by the re-synchronization jump
width. PHS2[2..0] shall be ≥1 and ≤PHS1[2..0] (c.f. Section 16.2.3 “CAN Bit Timing” on page 143 and Section 16.4.3 “Baud
Rate” on page 148).
Tphs2 = Tscl (PHS2[2:0] + 1)
• Bit 3:1 – PHS12:0: Phase Segment 1
This phase is used to compensate for phase edge errors. This segment may be lengthened by the re-synchronization jump
width.
Tphs1 = Tscl (PHS1[2:0] + 1)
• Bit 0 – SMP: Sample Point(s)
This option allows to filter possible noise on TxCAN input pin.
●
●
0 - the sampling will occur once at the user configured sampling point - SP.
1 - with three-point sampling configuration the first sampling will occur two TclkIO clocks before the user configured
sampling point - SP, again at one TclkIO clock before SP and finally at SP. Then the bit level will be determined by a
majority vote of the three samples.
‘SMP=1’ configuration is not compatible with ‘BRP[5:0]=0’ because TQ = TclkIO.
If BRP = 0, SMP must be cleared.
164
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
