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ATMEGA16M1-15MZ 参数 Datasheet PDF下载

ATMEGA16M1-15MZ图片预览
型号: ATMEGA16M1-15MZ
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 16KB FLASH 32QFN]
分类和应用: 微控制器
文件页数/大小: 318 页 / 7595 K
品牌: MICROCHIP [ MICROCHIP ]
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16.11 MOb Registers  
The MOb registers has no initial (default) value after RESET.  
16.11.1 CAN MOb Status Register - CANSTMOB  
Bit  
7
DLCW  
R/W  
-
6
TXOK  
R/W  
-
5
RXOK  
R/W  
-
4
BERR  
R/W  
-
3
SERR  
R/W  
-
2
CERR  
R/W  
-
1
FERR  
R/W  
-
0
AERR CANSTMOB  
Read/Write  
Initial Value  
R/W  
-
• Bit 7 – DLCW: Data Length Code Warning  
The incoming message does not have the DLC expected. Whatever the frame type, the DLC field of the CANCDMOB  
register is updated by the received DLC.  
• Bit 6 – TXOK: Transmit OK  
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB  
register.  
The communication enabled by transmission is completed. TxOK rises at the end of EOF field. When the controller is ready  
to send a frame, if two or more message objects are enabled as producers, the lower MOb index (0 to 14) is supplied first.  
• Bit 5 – RXOK: Receive OK  
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB  
register.  
The communication enabled by reception is completed. RxOK rises at the end of the 6th bit of EOF field. In case of two or  
more message object reception hits, the lower MOb index (0 to 14) is updated first.  
• Bit 4 – BERR: Bit Error (Only in Transmission)  
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB  
register.  
The bit value monitored is different from the bit value sent.  
Exceptions: the monitored recessive bit sent as a dominant bit during the arbitration field and the acknowledge slot detecting  
a dominant bit during the sending of an error frame.  
• Bit 3 – SERR: Stuff Error  
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB  
register.  
Detection of more than five consecutive bits with the same polarity. This flag can generate an interrupt.  
• Bit 2 – CERR: CRC Error  
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB  
register.  
The receiver performs a CRC check on every de-stuffed received message from the start of frame up to the data field. If this  
checking does not match with the de-stuffed CRC field, a CRC error is set.  
• Bit 1 – FERR: Form Error  
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB  
register.  
The form error results from one or more violations of the fixed form in the following bit fields:  
CRC delimiter.  
Acknowledgment delimiter.  
EOF  
ATmega16/32/64/M1/C1 [DATASHEET]  
167  
7647O–AVR–01/15  
 
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