16.10.7 CAN Status Interrupt MOb Registers - CANSIT2 and CANSIT1
Bit
7
-
6
-
5
SIT5
-
4
SIT4
-
3
SIT3
-
2
SIT2
-
1
SIT1
-
0
SIT0
-
CANSIT2
CANSIT1
-
-
Bit
15
R
0
14
R
0
13
R
12
R
11
R
10
R
9
8
Read/Write
Initial Value
Read/Write
Initial Value
R
R
0
0
0
0
0
0
R
0
R
0
R
R
R
R
R
R
0
0
0
0
0
0
• Bits 5:0 - SIT5:0: Status of Interrupt by MOb
●
●
0 - no interrupt.
1- MOb interrupt.
Note:
Example: CANSIT2 = 0010 0001b: MOb 0 and 5 interrupts.
• Bit 15:6 – Reserved Bits
These bits are reserved for future use.
16.10.8 CAN Bit Timing Register 1 - CANBT1
Bit
7
-
6
BRP5
R/W
0
5
BRP4
R/W
0
4
BRP3
R/W
0
3
BRP2
R/W
0
2
BRP1
R/W
0
1
BRP0
R/W
0
0
-
CANBT1
Read/Write
Initial Value
-
-
-
-
• Bit 7– Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT1 is written.
• Bit 6:1 – BRP5:0: Baud Rate Prescaler
The period of the CAN controller system clock Tscl is programmable and determines the individual bit timing.
BRP[5:0] + 1
clkIOfrequency
------------------------------------
Tscl =
If ‘BRP[5..0]=0’, see Section 16.4.3 “Baud Rate” on page 148 and Section • “Bit 0 – SMP: Sample Point(s)” on page 164.
• Bit 0 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT1 is written.
16.10.9 CAN Bit Timing Register 2 - CANBT2
Bit
7
-
6
SJW1
R/W
0
5
SJW0
R/W
0
4
-
3
PRS2
R/W
0
2
PRS1
R/W
0
1
PRS0
R/W
0
0
-
CANBT2
Read/Write
Initial Value
-
-
-
-
-
-
• Bit 7– Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT2 is written.
ATmega16/32/64/M1/C1 [DATASHEET]
163
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
