Table 13-3 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct or the phase and
frequency correct, PWM mode.
Table 13-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1)
COMnA1/COMnB1
COMnA0/COMnB0
Description
0
0
Normal port operation, OCnA/OCnB disconnected.
WGMn3:0 = 8, 9 10 or 11: Toggle OCnA on compare match,
OCnB disconnected (normal port operation). For all other WGM1
settings, normal port operation, OC1A/OC1B disconnected.
0
1
Clear OCnA/OCnB on compare match when up-counting. Set
OCnA/OCnB on compare match when downcounting.
1
1
0
1
Set OCnA/OCnB on compare match when up-counting. Clear
OCnA/OCnB on compare match when downcounting.
Note:
1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. See Section 13.8.4
“Phase Correct PWM Mode” on page 105 for more details.
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB register, these bits control the counting sequence of the counter, the
source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 13-4. Modes of
operation supported by the Timer/Counter unit are: normal mode (counter), clear timer on compare match (CTC) mode, and
three types of Pulse Width Modulation (PWM) modes (see Section 13. “16-bit Timer/Counter1 with PWM” on page 92).
Table 13-4. Waveform Generation Mode Bit Description(1)
WGMn2 WGMn1 WGMn0
Mode WGMn3 (CTCn) (PWMn1) (PWMn0) Timer/Counter Mode of Operation TOP
Update of
OCRnx at
TOVn Flag
Set on
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Normal
0xFFFF
0x00FF
0x01FF
0x03FF
OCRnA
0x00FF
0x01FF
0x03FF
Immediate
TOP
MAX
PWM, phase correct, 8-bit
PWM, phase correct, 9-bit
PWM, phase correct, 10-bit
CTC
BOTTOM
BOTTOM
BOTTOM
MAX
2
TOP
3
TOP
4
Immediate
TOP
5
Fast PWM, 8-bit
Fast PWM, 9-bit
Fast PWM, 10-bit
TOP
6
TOP
TOP
7
TOP
TOP
8
PWM, phase and frequency correct ICRn
PWM, phase and frequency correct OCRnA
BOTTOM
BOTTOM
TOP
BOTTOM
BOTTOM
BOTTOM
BOTTOM
MAX
9
10
11
12
13
14
15
Note:
PWM, phase correct
PWM, phase correct
CTC
ICRn
OCRnA
ICRn
–
TOP
Immediate
–
(Reserved)
–
Fast PWM
ICRn
OCRnA
TOP
TOP
Fast PWM
TOP
TOP
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality
and location of these bits are compatible with previous versions of the timer.
ATmega16/32/64/M1/C1 [DATASHEET]
111
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
