13.10 16-bit Timer/Counter Register Description
13.10.1 Timer/Counter1 Control Register A – TCCR1A
Bit
7
6
5
4
3
–
2
–
1
0
COM1A1 COM1A0 COM1B1 COM1B0
WGM11 WGM10 TCCR1A
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
The COMnA1:0 and COMnB1:0 control the output compare pins (OCnA and OCnB respectively) behavior. If one or both of
the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is connected
to. If one or both of the COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the I/O
pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnA or OCnB pin
must be set in order to enable the output driver.
When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits
setting. Table 13-1 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to a Normal or a CTC mode (non-
PWM).
Table 13-1. Compare Output Mode, non-PWM
COMnA1/COMnB1
COMnA0/COMnB0
Description
0
0
1
1
0
1
0
1
Normal port operation, OCnA/OCnB disconnected.
Toggle OCnA/OCnB on compare match.
Clear OCnA/OCnB on compare match (set output to low level).
Set OCnA/OCnB on compare match (set output to high level).
Table 13-2 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode.
Table 13-2. Compare Output Mode, Fast PWM(1)
COMnA1/COMnB1
COMnA0/COMnB0
Description
0
0
Normal port operation, OCnA/OCnB disconnected.
WGMn3:0 = 14 or 15: Toggle OC1A on compare match, OC1B
disconnected (normal port operation). For all other WGM1
settings, normal port operation, OC1A/OC1B disconnected.
0
1
1
1
0
1
Clear OCnA/OCnB on compare match, set OCnA/OCnB at TOP
Set OCnA/OCnB on compare match, clear OCnA/OCnB at TOP
Note:
1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. In this case the com-
pare match is ignored, but the set or clear is done at TOP. See Section 13.8.3 “Fast PWM Mode” on page 103
for more details.
110
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
