Figure 13-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM
mode the OCRnx register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by
BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn Flag at BOTTOM.
Figure 13-12.Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn
(clkI/O/1)
TCNTn
TOP - 1
TOP - 1
TOP
TOP
BOTTOM
TOP - 1
BOTTOM + 1
TOP - 2
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOVn (FPWM)
and ICFn
(if used as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
Figure 13-13 shows the same timing data, but with the prescaler enabled.
Figure 13-13.Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
TOP - 1
TOP - 1
TOP
TOP
BOTTOM
TOP - 1
BOTTOM + 1
TOP - 2
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOVn (FPWM)
and ICFn
(if used as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
ATmega16/32/64/M1/C1 [DATASHEET]
109
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
