The extreme values for the OCRnx register represents special cases when generating a PWM waveform output in the phase
correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the
output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If
OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty
cycle.
13.9 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a clock enable signal in the
following figures. The figures include information on when Interrupt Flags are set, and when the OCRnx register is updated
with the OCRnx buffer value (only for modes utilizing double buffering). Figure 13-10 shows a timing diagram for the setting
of OCFnx.
Figure 13-10.Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling
clkI/O
clkTn
(clkI/O/1)
TCNTn
OCRnx
OCFnx
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
Figure 13-11 shows the same timing data, but with the prescaler enabled.
Figure 13-11.Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCFnx
OCRnx Value
108
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
