13.10.9 Timer/Counter1 Interrupt Flag Register – TIFR1
Bit
7
–
6
–
5
4
–
3
–
2
1
0
TOV1
R/W
0
ICF1
R/W
0
OCF1B OCF1A
TIFR1
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R/W
0
R/W
0
• Bit 7, 6 – Res: Reserved Bits
These bits are unused bits in the ATmega16/32/64/M1/C1, and will always read as zero.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the input capture register (ICR1) is set by the WGMn3:0
to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value.
ICF1 is automatically cleared when the input capture interrupt vector is executed. Alternatively, ICF1 can be cleared by
writing a logic one to its bit location.
• Bit 4, 3 – Res: Reserved Bits
These bits are unused bits in the ATmega16/32/64/M1/C1, and will always read as zero.
• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the output compare register B (OCR1B).
Note that a forced output compare (FOC1B) strobe will not set the OCF1B flag.
OCF1B is automatically cleared when the output compare match B interrupt vector is executed. Alternatively, OCF1B can be
cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the output compare register A (OCR1A).
Note that a forced output compare (FOC1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the output compare match A interrupt vector is executed. Alternatively, OCF1A can be
cleared by writing a logic one to its bit location.
• Bit 0 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In normal and CTC modes, the TOV1 flag is set when the
timer overflows. Refer to Table 13-4 on page 111 for the TOV1 flag behavior when using another WGMn3:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 overflow interrupt vector is executed. Alternatively, TOV1 can be
cleared by writing a logic one to its bit location.
ATmega16/32/64/M1/C1 [DATASHEET]
115
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
