The Timer/Counter overflow flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or ICRn is
used for defining the TOP value, the OCnA or ICFn flag is set accordingly at the same timer clock cycle as the OCRnx
registers are updated with the double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each
time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the
compare registers. If the TOP value is lower than any of the compare registers, a compare match will never occur between
the TCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCRnx Registers are written. As the third period shown in Figure 13-8 illustrates, changing the TOP actively while the
Timer/Counter is running in the phase correct mode can result in an unsymmetrical output.
The reason for this can be found in the time of update of the OCRnx Register. Since the OCRnx update occurs at TOP, the
PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP
value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes
of the period will differ in length. The difference in length gives the unsymmetrical result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP
value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the
two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the
COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the
COMnx1:0 to three (See Table on page 111). The actual OCnx value will only be visible on the port pin if the data direction
for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx register at
the compare match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx register at
compare match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using
phase correct PWM can be calculated by the following equation:
f
clk_I/O
---------------------------
f
=
OCnxPCPWM
2 N TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx register represent special cases when generating a PWM waveform output in the phase
correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the
output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic
values. If OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output will toggle with a
50% duty cycle.
13.8.5 Phase and Frequency Correct PWM Mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGMn3:0 = 8 or 9)
provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct
PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from
BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting compare output mode, the output compare
(OCnx) is cleared on the compare match between TCNTn and OCRnx while upcounting, and set on the compare match
while downcounting. In inverting compare output mode, the operation is inverted. The dual-slope operation gives a lower
maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-
slope PWM modes, these modes are preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCRnx
Register is updated by the OCRnx buffer register, (see Figure 13-8 and Figure 13-9 on page 107).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The
minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA
set to MAX). The PWM resolution in bits can be calculated using the following equation:
logTOP + 1
---------------------------------
=
R
PFCPWM
log2
106
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
