93C06/46
3.8
ERASE All (ERAL)
The entire chip will be erased to logical "1s" if this
instruction is received by the device and it is in the
EWEN mode. The ERAL cycle is completely self-timed
and commences after the last dummy address bit has
been clocked in.
ERAL takes 15 ms maximum.
FIGURE 3-5:
CLK
ERASE ALL
T
CSL
CS
SB
DI
1
0
0
1
0
X
X
X
X
T
SV
DO
HIGH - Z
T
WC
BSY
RDY
T
DDZ
OP1
OP2
STATUS
CHECK
T
CSL
NEW INSTRUCTION
OR STANDBY (CS = 0)
3.9
WRITE All (WRAL)
Note:
The entire chip will be written with the data specified in
that command. The WRAL cycle is completely self-
timed and commences after the rising edge of the CLK
for the last data bit (DO). WRAL takes 15 ms maxi-
mum.
The WRAL does not include an automatic
ERASE cycle for the chip. Therefore, the
WRAL instruction must be preceded by an
ERAL instruction and the chip must be in
the EWEN status in both cases.
The WRAL instruction is used for testing and/or device
initialization.
FIGURE 3-6:
CLK
WRITE ALL
T
CSL
CS
SB
DI
1
0
0
0
1
X
X
X
X
T
SV
DO
HIGH - Z
T
WC
BSY
RDY
OP1
OP2
D15
D0
STATUS
CHECK
T
CSL
NEW INSTRUCTION
OR STANDBY (CS = 0)
©
1995 Microchip Technology Inc.
DS11179C-page 7
MICROCHIP [ MICROCHIP TECHNOLOGY ]
