93C06/46
3.4
READ Mode
3.5
WRITE Mode
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
bit (logical 0) precedes the 16-bit output string. The
output data changes during the HIGH state of the sys-
tem clock (CLK). The dummy bit is output TPD after
the positive edge of CLK, which was used to clock in
the last address bit (A0). Therefore, care must be
taken if DI and DO are connected together as a bus
contention will occur for one clock cycle if A0 has been
a one.
DO will go into HIGH-Z mode with the positive edge of
the next CLK cycle. This follows the output of the last
data bit D0 or the low going edge of CS, which ever
occurs first.
DO remains stable between CLK cycles for an unlim-
ited time as long as CS stays HIGH.
The most significant data bit (D15) is always output
first, followed by the lower significant bits (D14 - D0).
The WRITE instruction is followed by 16 bits of data
which are written into the specified address. The most
significant data bit (D15) has to be clocked in first, fol-
lowed by the lower significant data bits (D14 – D0). If
a WRITE instruction is recognized by the device and all
data bits have been clocked in, the device performs an
automatic ERASE cycle on the specified address
before the data are written. The WRITE cycle is com-
pletely self-timed and commences automatically after
the rising edge of the CLK for the last data bit (D0).
The WRITE cycle takes 2 ms maximum.
FIGURE 3-1:
CLK
READ MODE
T
CSL
CS
SB
DI
1
DO
1
0
T
PD
HIGH - Z
0
D15
D0
T
DDZ
OP1
OP2
A5
A4
A3
A0
NEW INSTRUCTION
OR STANDBY (CS = 0)
FIGURE 3-2:
CLK
WRITE MODE
T
CSL
CS
SB
DI
1
0
1
T
SV
DO
HIGH - Z
T
WC
BSY
OP1
OP2
A5
A4
A3
A0
D15
D0
STATUS
CHECK
T
CSL
T
DDZ
RDY
NEW INSTRUCTION
OR STANDBY (CS = 0)
©
1995 Microchip Technology Inc.
DS11179C-page 5
MICROCHIP [ MICROCHIP TECHNOLOGY ]
