93C06/46
TABLE 1-3:
AC CHARACTERISTICS
Parameter
Clock frequency
Clock high time
Clock low time
Chip select setup time
Chip select hold time
Chip select low time
Data input setup time
Data input hold time
Data output delay time
Data output disable time (from CS = low)
Data output disable time (from last clock)
Status valid time
Program cycle time (Auto Erase and Write)
Erase cycle time
Symbol
F
CLK
T
CKH
T
CKL
T
CSS
T
CSH
T
CSL
T
DIS
T
DIH
T
PD
T
CZ
T
DDZ
T
SV
T
WC
T
EC
500
500
50
0
100
100
100
—
0
0
—
—
—
Min
Max
1
—
—
—
—
—
—
—
400
100
400
100
2
15
1
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
CL = 100 pF
CL = 100 pF
CL = 100 pF
CL = 100 pF
For ERAL and WRAL
Conditions
2.0
2.1
PIN DESCRIPTION
Chip Select (CS)
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a start condition, the specified num-
ber of clock cycles (respectively LOW to HIGH transi-
tions of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (see instruc-
tion set truth table). CLK and DI then become “Don't
Care” inputs waiting for a new start condition to be
detected.
Note:
CS must go LOW between consecutive
instructions.
A HIGH level selects the device. A LOW level dese-
lects the device and forces it into standby mode. How-
ever, a programming cycle which is already initiated
and/or in progress will be completed, regardless of the
CS input signal. If CS is brought LOW during a pro-
gram cycle, the device will go into standby mode as
soon as the programming cycle is completed.
CS must be LOW for 100 ns minimum (T
CSL
) between
consecutive instructions. If CS is LOW, the internal
control logic is held in a RESET status.
2.3
Data In (DI)
2.2
Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93C06/46.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be contin-
ued anytime (with respect to clock HIGH time (T
CKH
)
and clock LOW time (T
CKL
). This gives the controlling
master freedom in preparing opcode, address and
data.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status. (i.e., waiting
for START condition).
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4
Data Out (DO)
Data Out is used in the READ mode to output data
synchronously with the CLK input (T
PD
after the posi-
tive edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought HIGH after being LOW for minimum chip select
LOW time (T
CSL
) from the falling edge of the CLK which
clocked in the last DI bit (D0 for WRITE, A0 for ERASE)
and an ERASE or WRITE operation has been initiated.
©
1995 Microchip Technology Inc.
DS11179C-page 3
MICROCHIP [ MICROCHIP TECHNOLOGY ]
