93C06/46
The status signal is not available on DO, if CS is held
LOW or HIGH during the entire WRITE or ERASE
cycle. In all other cases DO is in the HIGH-Z mode. If
status is checked after the WRITE/ERASE cycle, a
pull-up resistor on DO is required to read the READY
signal.
DI and DO can be connected together to perform a 3-
wire interface (CS, CLK, DI/DO).
Care must be taken with the leading dummy zero which
is outputted after a READ command has been
detected. Also, the controlling device must not drive
the DI/DO bus during Erase and Write cycles if the
READY/BUSY status information is outputted by the
93C06/46.
INSTRUCTION SET - 93C06
Instruction
READ
WRITE
ERASE
EWEN
EWDS
ERAL
WRAL
Start BIT
1
1
1
1
1
1
1
Opcode
OP1 OP2
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
Address
A3
A3
A3
X
X
X
X
A2
A2
A2
X
X
X
X
A1 A0
A1 A0
A1 A0
X X
X X
X X
X X
Number of
Data In
—
D15 - D0
—
—
—
—
D15 - D0
Data Out
D15 - D0
(RDY/BSY)
(RDY/BSY)
High-Z
High-Z
(RDY/BSY)
(RDY/BSY)
Req. CLK
Cycles
25
25
9
9
9
9
25
INSTRUCTION SET - 93C46
Instruction
READ
WRITE
ERASE
EWEN
EWDS
ERAL
WRAL
Start BIT
1
1
1
1
1
1
1
Opcode
OP1 OP2
1
0
1
0
0
0
0
0
1
1
0
0
0
0
A5
A5
A5
1
0
1
0
Address
A4
A4
A4
1
0
0
1
A3
A3
A3
X
X
X
X
A2
A2
A2
X
X
X
X
A1
A1
A1
X
X
X
X
A0
A0
A0
X
X
X
X
Number of
Data In
—
D15 - D0
—
—
—
—
D15 - D0
Data Out
D15 - D0
(RDY/BSY)
(RDY/BSY)
High-Z
High-Z
(RDY/BSY)
(RDY/BSY)
Req. CLK
Cycles
25
25
9
9
9
9
25
3.0
3.1
FUNCTIONAL DESCRIPTION
START Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
that precedes the READ operation, if A0 is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin.
3.3
Data Protection
During power-up, all modes of operation are inhibited
until V
CC
has reached 2.8V. During power-down, the
source data protection circuitry acts to inhibit all modes
when V
CC
has fallen below 2.8V.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed. After programming is completed, the
EWDS instruction offers added protection against unin-
tended data changes.
3.2
DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
DS11179C-page 4
©
1995 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
