93C06/46
3.6
ERASE Mode
The ERASE instruction forces all the data bits of the
specified address to logical "1s". The ERASE cycle is
completely self-timed and commences automatically
after the last address bit has been clocked in.
The ERASE cycle takes 1 ms maximum.
FIGURE 3-3:
CLK
ERASE MODE
T
CSL
CS
SB
DI
1
1
1
T
SV
DO
HIGH - Z
T
EC
BSY
OP1
OP2
A5
A4
A3
A0
STATUS
CHECK
T
CSL
T
DDZ
RDY
NEW INSTRUCTION
OR STANDBY (CS = 0)
3.7
ERASE/WRITE Enable/Disable
(EWEN, EWDS)
The device is automatically in the ERASE/WRITE
Disable mode (EWDS) after power-up. Therefore,
an EWEN instruction has to be performed before any
ERASE, WRITE, ERAL, WRAL instruction is exe-
cuted by the device. For added data protection, the
device should be put in the ERASE/WRITE Disable
mode (EWDS) after programming operations are
completed.
FIGURE 3-4:
CLK
ERASE/WRITE ENABLE/DISABLE
T
CSL
CS
SB
DI
1
0
0
0
1
0
1
X
X
X
X
(EWDS)
(EWEN)
OP1
OP2
SB
NEW INSTRUCTION
OR STANDBY (CS = 0)
DS11179C-page 6
©
1995 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
