24AA64/24LC64
2.0
2.1
PIN DESCRIPTIONS
A0, A1, A2 Chip Address Inputs
4.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
The A0,A1,A2 inputs are used by the 24xx64 for multi-
ple device operation. The levels on these inputs are
compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight devices may be connected to the same bus
by using different chip select bit combinations. These
inputs must be connected to either V
CC
or V
SS
.
2.2
SDA Serial Data
4.1
Bus not Busy (A)
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pullup
resistor to V
CC
(typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz)
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
Both data and clock lines remain HIGH.
4.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
4.3
Stop Data Transfer (C)
2.3
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must end with a STOP condition.
4.4
Data Valid (D)
2.4
WP
This pin can be connected to either Vss, Vcc or left
floating. An internal pull-down resistor on this pin will
keep the device in the unprotected state if left floating.
If tied to Vss or left floating, normal memory operation
is enabled (read/write the entire memory 0000-1FFF).
If tied to V
CC
, WRITE operations are inhibited. Read
operations are not affected.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.0
FUNCTIONAL DESCRIPTION
The 24xx64 supports a bi-directional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be con-
trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions while the 24xx64
works as a slave. Both master and slave can operate as
a transmitter or receiver but the master device deter-
mines which mode is activated.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
Note:
The 24xx64 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
case, the slave (24xx64) will leave the data line HIGH
to enable the master to generate the STOP condition.
©
1998 Microchip Technology Inc.
DS21189B-page 4
MICROCHIP [ MICROCHIP TECHNOLOGY ]
