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24LC64 参数 Datasheet PDF下载

24LC64图片预览
型号: 24LC64
PDF下载: 下载PDF文件 查看货源
内容描述: 64K I 2 C ⑩ CMOS串行EEPROM [64K I 2 C ⑩ CMOS Serial EEPROM]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 12 页 / 184 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
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24AA64/24LC64
TABLE 1-3
AC CHARACTERISTICS
Tamb = -40
°
C to +85
°
C
Tamb = -40
°
C to 125
°
C
Conditions
4.5V
V
CC
5.5V (E Temp range)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
4.5V
V
CC
5.5V (E Temp range)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
4.5V
V
CC
5.5V (E Temp range)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
4.5V
V
CC
5.5V (E Temp range)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
4.5V
V
CC
5.5V (E Temp range)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
4.5V
V
CC
5.5V (E Temp range)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
4.5V
V
CC
5.5V (E Temp range)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
4.5V
V
CC
5.5V (E Temp range)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
4.5V
V
CC
5.5V (E Temp range)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
4.5V
V
CC
5.5V (E Temp range)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
4.5V
V
CC
5.5V (E Temp range)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
4.5V
V
CC
5.5V (E Temp range)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
C
B
100 pF (Note 1)
All parameters apply across the spec-
Industrial (I):
V
CC
= +1.8V to 5.5V
ified operating ranges unless other-
Automotive (E): V
CC
= +4.5V to 5.5V
wise noted.
Parameter
Clock frequency
Symbol
F
CLK
Min
4000
4000
600
4700
4700
1300
4000
4000
600
4700
4700
600
0
250
250
100
4000
4000
600
4000
4000
600
4700
4000
1300
4700
4700
1300
10
1M
Max
100
100
400
1000
1000
300
300
3500
3500
900
250
50
5
Units
kHz
Clock high time
T
HIGH
ns
Clock low time
T
LOW
ns
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
T
R
ns
T
F
T
HD
:
STA
ns
ns
START condition setup time
T
SU
:
STA
ns
Data input hold time
Data input setup time
T
HD
:
DAT
T
SU
:
DAT
ns
ns
STOP condition setup time
T
SU
:
STO
ns
WP setup time
T
SU
:
WP
ns
WP hold time
T
HD
:
WP
ns
Output valid from clock
Bus free time: Time the bus must be
free before a new transmission can
start
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or page)
Endurance
Note 1:
2:
3:
4:
T
AA
ns
T
BUF
ns
T
OF
T
SP
T
WC
ns
ns
ms
cycles
25°C, V
CC
= 5.0V, Block Mode (Note 4)
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.
©
1998 Microchip Technology Inc.
DS21189B-page 3