24AA64/24LC64
TABLE 1-3
AC CHARACTERISTICS
All parameters apply across the spec-
ified operating ranges unless other-
wise noted.
Industrial (I):
Automotive (E): VCC = +4.5V to 5.5V
VCC = +1.8V to 5.5V
Tamb = -40°C to +85°C
Tamb = -40°C to 125°C
Parameter
Symbol
FCLK
Min
Max
Units
kHz
Conditions
Clock frequency
—
—
—
100
100
400
4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
Clock high time
Clock low time
THIGH
TLOW
TR
4000
4000
600
—
—
—
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
4700
4700
1300
—
—
—
4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
SDA and SCL rise time
(Note 1)
—
—
—
1000
1000
300
4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
SDA and SCL fall time
TF
—
300
ns
ns
(Note 1)
START condition hold time
THD:STA
4000
4000
600
—
—
—
4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
START condition setup time
TSU:STA
4700
4700
600
—
—
—
ns
4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
Data input hold time
Data input setup time
THD:DAT
TSU:DAT
0
—
ns
ns
(Note 2)
250
250
100
—
—
—
4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
STOP condition setup time
WP setup time
TSU:STO
TSU:WP
THD:WP
TAA
4000
4000
600
—
—
—
ns
ns
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
4000
4000
600
—
—
—
4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
WP hold time
4700
4000
1300
—
—
—
4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
Output valid from clock
(Note 2)
—
—
—
3500
3500
900
4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
Bus free time: Time the bus must be
free before a new transmission can
start
TBUF
4700
4700
1300
—
—
—
4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
Output fall time from VIH
minimum to VIL maximum
TOF
TSP
TWC
10
250
ns
ns
C ≤ 100 pF (Note 1)
B
Input filter spike suppression
(SDA and SCL pins)
—
50
(Notes 1 and 3)
Write cycle time (byte or page)
Endurance
—
5
ms
1M
—
cycles 25°C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. C = total capacitance of one bus line in pF.
B
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.
1998 Microchip Technology Inc.
DS21189B-page 3
MICROCHIP [ MICROCHIP ]
