24C01SC/02SC
7.4
Noise Protection
The 24C01SC/02SC employs a V
CC
threshold detector
circuit which disables the internal erase/write logic if the
V
CC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
FIGURE 7-1:
CURRENT ADDRESS READ
S
T
A
R
T
CONTROL
BYTE
S
T
O
P
BUS ACTIVITY
MASTER
DATA n
SDA LINE
S
A
C
K
N
O
A
C
K
P
BUS ACTIVITY
FIGURE 7-2:
RANDOM READ
CONTROL
BYTE
WORD
ADDRESS (n)
S
T
A
R
T
CONTROL
BYTE
S
T
O
P
S
T
BUS ACTIVITY
A
MASTER
R
T
SDA LINE
DATA n
S
A
C
K
A
C
K
S
A
C
K
N
O
A
C
K
P
BUS ACTIVITY
FIGURE 7-3:
SEQUENTIAL READ
CONTROL
BYTE
A
C
K
A
C
K
A
C
K
S
T
O
P
BUS ACTIVITY
MASTER
SDA LINE
P
A
C
K
DATA n
DATA n + 1
DATA n + 2
DATA n + X
N
O
A
C
K
BUS ACTIVITY
©
1996 Microchip Technology Inc.
Preliminary
DS21170A-page 7
MICROCHIP [ MICROCHIP TECHNOLOGY ]
