24C01SC/02SC
TABLE 1-3:
AC CHARACTERISTICS
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
Symbol
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
Min.
—
600
1300
—
—
600
600
0
100
600
—
1300
Max.
400
—
—
300
300
—
—
—
—
—
900
—
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 2)
Time the bus must be free
before a new transmission can
start
(Note 1), CB
≤
100 pF
(Note 3)
Byte or Page mode
25
°
C, Vcc = 5V, Block Mode
(Note 1)
(Note 1)
After this period the first clock
pulse is generated
Only relevant for repeated
START condition
(Note 2)
Remarks
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
T
OF
T
SP
T
WR
—
20 +0.1
CB
—
—
10
6
250
50
10
—
ns
ns
ms
cycles
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2:
BUS TIMING DATA
T
F
T
HIGH
T
LOW
T
R
SCL
T
SU
:
STA
SDA
IN
T
HD
:
STA
T
SP
T
AA
SDA
OUT
T
HD
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
©
1996 Microchip Technology Inc.
Preliminary
DS21170A-page 3
MICROCHIP [ MICROCHIP TECHNOLOGY ]
