PIC12CE67X
8.5
A/D Operation During Sleep
8.7
Effects of a RESET
The A/D module can operate during SLEEP mode.This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed the GO/DONE bit will be cleared, and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted. The value that is in the ADRES
register is not modified for a Reset. The ADRES regis-
ter will contain unknown data after a Power-on Reset.
8.8
Connection Considerations
If the input voltage exceeds the rail values (VSS or VDD)
by greater than 0.2V, then the accuracy of the conver-
sion is out of specification.
Note: For the PIC12CE67X, care must be taken
when using the GP4 pin in A/D conver-
sions due to its proximity to the OSC1 pin.
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
An external RC filter is sometimes added for anti-alias-
ing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept under the 10 kΩ recommended specification. Any
external components connected (via hi-impedance) to
an analog input pin (capacitor, zener diode, etc.) should
have very little leakage current at the pin.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in SLEEP, the GO/DONE bit
must be set, followed by the SLEEPinstruc-
tion.
8.9
Transfer Function
The ideal transfer function of the A/D converter is as fol-
lows: the first transition occurs when the analog input
voltage (VAIN) is 1 LSb (or Analog VREF / 256)
(Figure 8-5).
8.6
A/D Accuracy/Error
FIGURE 8-5: A/D TRANSFER FUNCTION
The overall accuracy of the A/D is less than ± 1 LSb for
VDD = 5V ± 10% and the analog VREF = VDD.This over-
all accuracy includes offset error, full scale error, and
integral error. The A/D converter is guaranteed to be
monotonic. The resolution and accuracy may be less
when either the analog reference (VDD) is less than
5.0V or when the analog reference (VREF) is less than
VDD.
FFh
FEh
The maximum pin leakage current is ± 5 µA.
In systems where the device frequency is low, use of
the A/D RC clock is preferred. At moderate to high fre-
quencies, TAD should be derived from the device oscil-
lator. TAD must not violate the minimum and should be
≤ 8 µs for preferred operation. This is because TAD,
when derived from TOSC, is kept away from on-chip
phase clock transitions.This reduces, to a large extent,
the effects of digital switching noise.This is not possible
with the RC derived clock. The loss of accuracy due to
digital switching noise can be significant if many I/O
pins are active.
04h
03h
02h
01h
00h
Analog input voltage
In systems where the device will enter SLEEP mode
after the start of the A/D conversion, the RC clock
source selection is required. In this mode, the digital
noise from the modules in SLEEP are stopped. This
method gives high accuracy.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 43
MICROCHIP [ MICROCHIP ]
