PIC12CE67X
FIGURE 6-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(C)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
FIGURE 6-2: ACKNOWLEDGE TIMING
Acknowledge
Bit
1
2
3
4
5
6
7
8
9
1
2
3
SCL
SDA
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
6.2
Device Addressing
FIGURE 6-3: CONTROL BYTE FORMAT
Read/Write Bit
After generating a START condition, the processor
transmits a control byte consisting of a EEPROM
address and a Read/Write bit that indicates what type
of operation is to be performed.The EEPROM address
consists of a 4-bit device code (1010) followed by three
don't care bits.
Device Select
Don’t Care
Bits
Bits
S
1
0
1
0
X
X
X R/W ACK
The last bit of the control byte determines the operation
to be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. (Figure 6-3). The bus is monitored for its cor-
responding EEPROM address all the time. It generates
an acknowledge bit if the EEPROM address was true
and it is not in a programming mode.
EEPROM Address
Acknowledge Bit
Start Bit
DS40181B-page 28
Preliminary
1998 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
