PIC12CE67X
4.2.2.5
PIR1 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
This register contains the individual flag bits for the
Peripheral interrupts.
FIGURE 4-7: PIR1 REGISTER (ADDRESS 0Ch)
U-0
—
R/W-0
ADIF
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6:
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5-0: Unimplemented: Read as '0'
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 19
MICROCHIP [ MICROCHIP ]
