KSZ8795CLX
TABLE 4-21: ACL INDIRECT REGISTERS FOR 14 BYTE ACL RULES
Address
Name
Description
Mode
Default
Port_ACL_0
ACL Port Register 0 (0x00)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x00 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Processing Field
7 - 4
3 - 0
Reserved
FRN[3:0]
—
RO
0x0
First Rule Number
R/W
0000
This is for the first rule number of the rule set.
There are total 16 entries per port in ACL rule table.
Each single rule can be set with other rule for a rule
set by the ACL port Register 12 (0x0c) and Regis-
ter 13 (0x0d).
Regardless single rule or rule set, have to assign
an entry for using which Action Field by FRN[3:0].
Port_ACL_1
ACL Port Register 1 (0x01)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x01 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields
7 - 6
5 - 4
Reserved
MD[1:0]
—
RO
00
00
MODE
R/W
00 = Disable the current rule list, no action taken
01 = Qualify rules for Layer 2 MAC header filtering
10 = Is used for Layer 3 IP address filtering
11 = Performs Layer 4 TCP port number/protocol
filtering
2016 Microchip Technology Inc.
DS00002112A-page 87
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