KSZ8795CLX
TABLE 4-2:
DIRECT REGISTERS (CONTINUED)
Address
Contents
0xBF
0xC0-0xCE
0xCF
Reserved (Factory Testing Register): Transmit Queue Remap Base Register
Port 2 Control Registers
Reserved (Factory Testing Register)
Port 3 Control Registers
0xD0-0xDE
0xDF
Reserved (Factory Testing Register)
Port 4 Control Registers
0xE0-0xEE
0xEF
Reserved (Factory Testing Register)
Port 5 Control Registers
0xF0-0xFE
0xFF
Reserved (Factory Testing Register)
TABLE 4-3:
Address
Register 0 (0x00): Chip ID0
7 0 Family ID
GLOBAL REGISTERS
Name
Description
Mode
Default
Chip family.
RO
0x87
Register 1 (0x01): Chip ID1/Start Switch
7 4
3 1
0
Chip ID
0x9 = 8795
—
RO
RO
0x9
0x0
1
Revision ID
Start Switch
1 = Start the switch function of the chip.
0 = Stop the switch function of the chip.
R/W
Register 2 (0x02): Global Control 0
7
New Back-Off Enable New Back-off algorithm designed for UNH
R/W
R/W
0
0
1 = Enable
0 = Disable
6
Global Soft Reset Enable Global Software Reset
1 = Enable to reset all FSM and data path (not con-
figuration).
0 = Disable reset.
Note: This reset will stop to receive packets if it is
being in the traffic. All registers keep their configu-
ration values.
5
Flush Dynamic MAC
Table
Flush the entire dynamic MAC table for RSTP. This
bit is self- clear (SC).
R/W
(SC)
0
1 = Trigger the flush dynamic MAC table operation.
0 = Normal operation.
Note: All the entries associated with a port that has
its learning capability being turned off (learning dis-
able) will be flushed. If you want to flush the entire
table, all ports learning capability must be turned
off.
DS00002112A-page 48
2016 Microchip Technology Inc.
MICREL [ MICREL SEMICONDUCTOR ]
