KSZ8795CLX
TABLE 4-1:
MAPPING OF FUNCTIONAL AREAS WITHIN THE ADDRESS SPACE (CONTINUED)
Register
Locations
Device Area
Description
0x17 - 0x4F
PHY1 to PHY4 MIIM Registers
Mapping to Those Port Registers’
Address Range
The same PHY registers as specified in IEEE 802.3
specification.
4.1
Register Map
TABLE 4-2:
DIRECT REGISTERS
Address
0x00-0x01
Contents
Family ID, Chip ID, Revision ID, and start switch Registers
Global Control Registers 0 – 11
0x02-0x0D
0x0E-0x0F
0x10-0x14
0x15
Global Power-Down Management Control Registers
Port 1 Control Registers 0 – 4
Port 1 Authentication Control Register
Port 1 Reserved (Factory Test Registers)
Port 1 Control/Status Registers
0x16-0x18
0x19-0x1F
0x20-0x24
0x25
Port 2 Control Registers 0 – 4
Port 2 Authentication Control Register
Port 2 Reserved (Factory Test Registers)
Port 2 Control/Status Registers
0x26-0x28
0x29-0x2F
0x30-0x34
0x35
Port 3 Control Registers 0 – 4
Port 3 Authentication Control Register
Port 3 Registered (Factory Test Registers)
Port 3 Control/Status Registers
0x36-0x38
0x39-0x3F
0x40-0x44
0x45
Port 4 Control Registers 0 – 4
Port 4 Authentication Control Register
Port 4 Reserved (Factory Test Registers)
Port 4 Control/Status Registers
0x46-0x48
0x49-0x4F
0x50-0x54
0x56-0x58
0x59-0x5F
0x60-0x67
0x68-0x6D
0x6E-0x6F
0x70-0x78
0x79-0x7B
0x7C-0x7D
0x7E-0x7F
0x80-0x87
0x88
Port 5 Control Registers 0 – 4
Port 5 Reserved (Factory Test Registers)
Port 5 Control/Status Registers
Reserved (Factory Testing Registers)
MAC Address Registers
Indirect Access Control Registers
Indirect Data Registers
Reserved (Factory Testing Registers)
Global Interrupt and Mask Registers
ACL Interrupt Status and Control Registers
Global Control Registers 12 – 19
Switch Self-Test Control Register
QM Global Control Registers
0x89-0x8F
0x90-0x9F
0xA0
Global TOS Priority Control Registers 0 - 15
Global Indirect Byte Register
0xA0-0xAF
0xB0-0xBE
Reserved (Factory Testing Registers)
Port 1 Control Registers
2016 Microchip Technology Inc.
DS00002112A-page 47
MICREL [ MICREL SEMICONDUCTOR ]
