KSZ8795CLX
4.0
DEVICE REGISTERS
The KSZ8795CLX device has a rich set of registers available to manage the functionality of the device. Access to these
registers is via the MIIM or SPI interfaces. Figure 4-1 provides a global picture of accessibility via the various interfaces
and addressing ranges from the perspective of each interface.
FIGURE 4-1:
INTERFACE AND REGISTER MAPPING
MIIM REGISTERS
PHYAD 1, 2, 3, 4
REGAD 0-5, 1D, 1F
PHY BLOCK
SWITCH CONFIG REGISTERS
00 ̢ 0xFF
17h - 4Fh
00h - FFh
SPI
The registers within the linear 0x00-0xFF address space are all accessible via the SPI interface by a CPU attached to
that bus. The mapping of the various functions within that linear address space is summarized in Table 4-1.
TABLE 4-1:
MAPPING OF FUNCTIONAL AREAS WITHIN THE ADDRESS SPACE
Register
Locations
Device Area
Description
0x00 - 0xFF
Switch Control and Configuration
Registers which control the overall functionality of the
Switch, MAC, and PHYs
0x6E - 0x6F
Indirect Control Registers
Registers used to indirectly address and access distinct
areas within the device.
- Management Information Base (MIB) Counters
- Static MAC Address Table
- Dynamic MAC Address Table
- VLAN Table
- PME Indirect Registers
- ACL Indirect Registers
- EEE Indirect Registers
0x70 - 0x78
Indirect Access Registers
Registers used to indirectly address and access four
distinct areas within the device.
- Management Information Base (MIB) Counters
- Static MAC Address Table
- Dynamic MAC Address Table
- VLAN Table
0xA0
Indirect Byte Access Registers
This indirect byte register is used to access:
- PME Indirect Registers
- ACL Indirect Registers
- EEE Indirect Registers
DS00002112A-page 46
2016 Microchip Technology Inc.
MICREL [ MICREL SEMICONDUCTOR ]
