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KSZ8795CLX 参数 Datasheet PDF下载

KSZ8795CLX图片预览
型号: KSZ8795CLX
PDF下载: 下载PDF文件 查看货源
内容描述: [Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces]
分类和应用: 局域网(LAN)标准
文件页数/大小: 132 页 / 1359 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
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KSZ8795CLX  
3.6.3  
RAPID SPANNING TREE SUPPORT  
There are three operational states of the discarding, learning, and forwarding assigned to each port for RSTP. Discard-  
ing ports do not participate in the active topology and do not learn MAC addresses. Ports in the learning states learn  
MAC addresses, but do not forward user traffic. Ports in the forwarding states fully participate in both data forwarding  
and MAC learning. RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP configuration  
BPDUs with the exception of a type field set to “version 2” for RSTP and “version 0” for STP, and flag field carrying addi-  
tional information.  
TABLE 3-14: PORT SETTING AND SOFTWARE ACTIONS FOR RAPID SPANNING TREE  
Disable State  
Port Setting  
Software Action  
The state includes  
three states of the  
"Transmit enable = 0, The processor should not send any packets to the port. The switch  
Receive enable = 0, may still send specific packets to the processor (packets that match  
disable, blocking and Learning disable = 1." some entries in the static table with “overriding bit” set) and the pro-  
listening of STP.  
cessor should discard those packets. When disable the port’s learning  
capability (learning disable = ’1’), set the Register 1 Bit[5] and Bit[4]  
will flush rapidly with the port-related entries in the dynamic MAC  
table and static MAC table. Note: processor is connected to Port 5 via  
MII interface. Address learning is disabled on the port in this state.  
Learning State  
Port Setting  
Software Action  
Only packets to and “Transmit enable = 0, The processor should program the static MAC table with the entries  
from the processor  
are forwarded.  
Learning is enabled.  
Receive enable = 0, that it needs to receive (e.g., BPDU packets). The “overriding” bit  
Learning disable = 0.” should be set so that the switch will forward those specific packets to  
the processor. The processor may send packets to the port(s) in this  
state (see “Tail Tagging Mode” section for details). Address learning is  
enabled on the Port in this state.  
Forwarding State  
Port Setting  
Software Action  
Packets are for-  
“Transmit enable = 1, The processor should program the static MAC table with the entries  
warded and received Receive enable = 1, that it needs to receive (e.g., BPDU packets). The “overriding” bit  
normally. Learning is Learning disable = 0.” should be set so that the switch will forward those specific packets to  
enabled.  
the processor. The processor may send packets to the port(s) in this  
state (see “Tail Tagging Mode” section for details). Address learning is  
enabled on the port in this state.  
3.6.4  
TAIL TAGGING MODE  
The tail tag is only seen and used by the Port 5 interface, which should be connected to a processor by the SW5-GMII,  
RGMII, MII, or RMII interfaces. One byte tail tagging is used to indicate the source/destination port on Port 5. Only bits  
[3:0] are used for the destination in the tail tagging byte. Other bits are not used. The tail tag feature is enabled by setting  
Register 12 Bit[1].  
FIGURE 3-10:  
TAIL TAG FRAME FORMAT  
DS00002112A-page 36  
2016 Microchip Technology Inc.  
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