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KSZ8795CLX 参数 Datasheet PDF下载

KSZ8795CLX图片预览
型号: KSZ8795CLX
PDF下载: 下载PDF文件 查看货源
内容描述: [Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces]
分类和应用: 局域网(LAN)标准
文件页数/大小: 132 页 / 1359 K
品牌: MICREL [ MICREL SEMICONDUCTOR ]
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KSZ8795CLX  
For MLD snooping, tail tag mode also needs to be enabled, so that the processor knows which port the MLD packet was  
received on. This is achieved by setting Register 12 Bit[1].  
3.6.7  
PORT MIRRORING SUPPORT  
The KSZ8795CLX supports “port mirror” as described in the following:  
3.6.7.1  
“Receive Only” Mirror on a Port  
All the packets received on the port will be mirrored on the sniffer port. For example, Port 1 is programmed to be “RX  
sniff,” and Port 5 is programmed to be the “sniffer port”. A packet, received on Port 1, is destined to Port 4 after the  
internal look-up. The KSZ8795CLX will forward the packet to both Port 4 and Port 5. KSZ8795CLX can optionally for-  
ward even “bad” received packets to Port 5.  
3.6.7.2  
“Transmit Only” Mirror on a Port  
All the packets transmitted on the port will be mirrored on the Sniffer Port. For example, Port 1 is programmed to be “TX  
sniff,” and Port 5 is programmed to be the “sniffer port”. A packet, received on any of the Ports, is destined to Port 1 after  
the internal look-up. The KSZ8795CLX will forward the packet to both Ports 1 and 5.  
3.6.7.3  
“Receive and Transmit” Mirror on Two Ports  
All the packets received on Port A and transmitted on Port B will be mirrored on the sniffer port. To turn on the “AND”  
feature, set Register 5 bit[0] to Bit[1]. For example, Port 1 is programmed to be “RX sniff,” Port 2 is programmed to be  
“TX sniff,” and Port 5 is programmed to be the “sniffer port”. A packet, received on Port 1, is destined to Port 4 after the  
internal look-up. The KSZ8795CLX will forward the packet to Port 4 only because it does not meet the “AND” condition.  
A packet, received on Port 1, is destined to Port 2 after the internal look-up. The KSZ8795CLX will forward the packet  
to both Port 2 and Port 5.  
Multiple ports can be selected to be “RX sniffed” or “TX sniffed.” Any port can be selected to be the “sniffer port.” All  
these per port features can be selected through the Port Control 1 Register.  
3.6.8  
VLAN SUPPORT  
The KSZ8795CLX supports 128 active VLANs and 4096 possible VIDs specified in IEEE 802.1q. The KSZ8795CLX  
provides a 128-entry VLAN table, which correspond to 4096 possible VIDs and converts to FID (7 bits) for address look-  
up max 128 active VLANs. If a non-tagged or null-VID-tagged packet is received, then the ingress port VID is used for  
look-up when 802.1q is enabled by the global Register 5 control 3 Bit[7]. In the VLAN mode, the look-up process starts  
from VLAN table look-up to determine whether the VID is valid. If the VID is not valid, the packet will then be dropped  
and its address will not be learned. If the VID is valid, FID is retrieved for further look-up by the static MAC table or  
dynamic MAC table. FID+DA is used to determine the destination port.  
Table 3-16 describes the different actions in different situations of DA and FID+DA in the static MAC table and dynamic  
MAC table after the VLAN table finishes a look-up action. FID+SA is used for learning purposes. Table 3-17 also  
describes learning in the dynamic MAC table when the VLAN table has done a look-up in the static MAC table without  
a valid entry.  
TABLE 3-16: FID+DA LOOK-UP IN VLAN MODE  
DA Found in  
Static MAC  
Table?  
FID+DA Found in  
Dynamic MAC Action  
Table?  
Use FID Flag?  
FID Match?  
No  
Don’t Care  
Don’t Care  
Don’t Care  
Don’t Care  
No  
Broadcast to the membership ports  
defined in the VLAN Table Bits[11:7].  
No  
Yes  
Send to the destination port defined in  
the Dynamic MAC Address Table  
Bits[58:56].  
Yes  
Yes  
0
1
Don’t Care  
No  
Don’t Care  
No  
Send to the destination port(s) defined  
in the Static MAC Address Table  
Bits[52:48].  
Broadcast to the membership ports  
defined in the VLAN Table Bits[11:7].  
DS00002112A-page 38  
2016 Microchip Technology Inc.  
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