KSZ8795CLX
TABLE 3-16: FID+DA LOOK-UP IN VLAN MODE (CONTINUED)
DA Found in
Static MAC
Table?
FID+DA Found in
Dynamic MAC Action
Table?
Use FID Flag?
FID Match?
Yes
1
No
Yes
Send to the destination port defined in
the Dynamic MAC Address Table
Bits[58:56].
Yes
1
Yes
Don’t Care
Send to the destination port(s) defined
in the Static MAC Address Table
bits[52:48].
TABLE 3-17: FID+SA LOOK-UP IN VLAN MODE
FID+SA Found in Dynamic MAC
Action
Table?
No
The FID+SA will be learned into the dynamic table.
Time stamp will be updated.
Yes
Advanced VLAN features are also supported in KSZ8795CLX, such as “VLAN ingress filtering” and “discard non PVID”
defined in bits [6:5] of the Port Control 2 Register. These features can be controlled on a per port basis.
3.6.9
RATE LIMITING SUPPORT
The KSZ8795CLX provides a fine resolution hardware rate limiting based on both bps (bit per second) and pps (packet
per second).
For bps, the rate step is 64 Kbps when the rate limit is less than 1Mbps rate for 100BT or 10BT, and 640 Kbps for 1000.
The rate step is 1Mbps when the rate limit is more than 1Mbps rate for 100BT or 10BT, 10 Mbps for 1000.
For pps, the rate step is 128 pps (besides the 1st one which is 64 pps) when the rate limit is less than 1Mbps rate for
100BT or 10BT, and 1280 pps (except the 1st one of 640 pps) for 1000. The rate step is 1Mbps when the rate limit is
more than 1.92 Kpps rate for 100BT or 10BT, 19.2 Kpps for 1000 (refer to Table 3-18).
The pps limiting is bounded by the bps rate for each pps setting. The mapping is shown in the 2nd column of Table 3-18.
TABLE 3-18: 10/100/1000 MBPS RATE SELECTION FOR THE RATE LIMIT
Bps Bound
Item
of pps
10 Mbps
100 Mbps
1000 Mbps
(Egress Only)
7d’0
7d’0
19.2 Kpps
10 Mbps
19.2 Kpps
100 Mbps
1.92 Mpps
1000 Mbps
7d’1 -
7d’10
7d’3, 6, (8x)10
1.92 Kpps
x code
1Mbps
x code
1.92 Kpps
x code
1Mbps
x code
19.2 Kpps
x code
10 Mbps
x code
7d’11 -
7d’100
7d’11 - 7d’100
—
10 Mbps
1.92 Kpps
x code
1Mbps
x code
19.2 Kpps
x code
10 Mbps
x code
7d’101
7d’102
7d’103
7d’104
7d’105
7d’106
7d’107
7d’108
7d’109
7d’110
7d’111
7d’112
7d’113
7d’102
7d’104
7d’108
7d’112
7d’001
7d’001
7d’001
7d’002
7d’002
7d’002
7d’002
7d’002
7d’003
64 pps
128 pps
256 pps
384 pps
512 pps
640 pps
768 pps
896 pps
1024 pps
1152 pps
1280 pps
1408 pps
1536 pps
64 Kbps
128 Kbps
192 Kbps
256 Kbps
320 Kbps
384 Kbps
448 Kbps
512 Kbps
576 Kbps
640 Kbps
704 Kbps
768 Kbps
832 Kbps
64 pps
128 pps
256 pps
384 pps
512 pps
640 pps
768 pps
896 pps
1024 pps
1152 pps
1280 pps
1408 pps
1536 pps
64 Kbps
128 Kbps
192 Kbps
256 Kbps
320 Kbps
384 Kbps
448 Kbps
512 Kbps
576 Kbps
640 Kbps
704 Kbps
768 Kbps
832 Kbps
640 pps
1280 pps
2560 pps
3840 pps
5120 pps
6400 pps
7680 pps
8960 pps
10240 pps
11520 pps
12800 pps
14080 pps
15360 pps
640 Kbps
1280 Kbps
1920 Kbps
2560 Kbps
3200 Kbps
3840 Kbps
4480 Kbps
5120 Kbps
5760 Kbps
6400 Kbps
7040 Kbps
7680 Kbps
8320 Kbps
2016 Microchip Technology Inc.
DS00002112A-page 39