KSZ8795CLX
TABLE 3-11: PORT 5 SW5-RGMII CLOCK DELAY CONFIGURATION WITH CONNECTION
PARTNER (CONTINUED)
Connection Partner
RGMII Clock
KSZ8795CLX
Register 86 Bits[4:3]
Configuration
RGMII Clock Mode
(Receive and
Transmit)
KSZ8795CLX RGMII
Clock Delay/Slew
Configuration
KSZ8795CLX
Register 86 (0x56)
Configuration
(Note 3-1)
Bit[4:3] = 01 Mode
Bit[4:3] = 00 Mode
Ingress Clock Input
Egress Clock Output
Ingress Clock Input
Egress Clock Output
Bit[4] = 0 (default)
Bit[3] = 0 (default)
Bit[4] = 0
No Delay
Delay
Delay
No Delay
Delay
No Delay
No Delay
Bit[3] = 0
Delay
Note 3-1
Processor with RGMII, an external GPHY or KSZ8795CLX back-to-back connection.
For example, two KSZ8795 devices are the back-to-back connection. If one device set bit[4:3] =’11’, another one should
set Bit[4:3] = ‘00’. If one device set Bit[4:3] =’01’, another one should set Bit[4:3] = ‘01’ too.
The RGMII mode is configured by the strap-in pin LED3 [1:0] =’11’ (default) or Register 86 (0x56) bits[1:0] = ‘11’ (default).
The speed choice is by the strap-in pin LED1_0 or Register 86 (0x56) Bit[6], the default speed is 1Gbps with bit[6] = 1’,
set bit[6] = ‘0’ is for 10/100 Mbps speed in RGMII mode. KSZ8795CLX provides Register 86 bits[4:3] with the adjustable
clock delay and Register 164 bits[6:4] with the adjustable drive strength for best RGMII timing on board level in 1Gbps
mode.
3.5.2.7
Port 5 GMAC5 SW5-RMII Interface
The RMII specifies a low pin count MII. The KSZ8795CLX supports RMII interface on Port 5 and provides the following
key characteristics:
• Supports 10 Mbps and 100 Mbps data rates.
• Uses a single 50 MHz clock reference (provided internally or externally): In internal mode, the chip provides a ref-
erence clock from the RXC5 pin to the opposite clock input pin for RMII interface when Port 5 RMII is set to clock
mode.
• In external mode, the chip receives 50 MHz reference clock on the TXC5/REFCLKI5 pin from an external oscilla-
tor or opposite RMII interface when the device is set to normal mode.
• Provides independent 2-bit wide (bi-bit) transmit and receive data paths.
For the details of SW5-RMII (Port 5 GMAC5 RMII) signal connection, see Table 3-12.
When the device is strapped to normal mode, the reference clock comes from the TXC5/REFCLKI5 pin and will be used
as the device’s clock source. Set the strap pin LED1_1 can select the device’s clock source either from the TXC5/REF-
CLKI5 pin or from an external 25 MHz crystal/oscillator clock on the XI/XO pin.
In internal mode, when using an internal 50 MHz clock as SW5-RMII reference clock, the KSZ8795CLX port 5 should
be set to clock mode by the strap pin LED2_1 or the port Register 86 bit[7]. The clock mode of the KSZ8795CLX device
will provide the 50 MHz reference clock to the port 5 RMII interface.
In external mode, when using an external 50 MHz clock source as SW5-RMII reference clock, the KSZ8795CLX port 5
should be set to normal mode by the strap pin LED2_1 or the port Register 86 bit[7]. The normal mode of the KSZ8795-
CLX device will start to work when it receives the 50 MHz reference clock on the TXC5/REFCLKI5 pin from an external
50 MHz clock source.
DS00002112A-page 32
2016 Microchip Technology Inc.
MICREL [ MICREL SEMICONDUCTOR ]
