欢迎访问ic37.com |
会员登录 免费注册
发布采购

W3H32M64EA-400SBM 参数 Datasheet PDF下载

W3H32M64EA-400SBM图片预览
型号: W3H32M64EA-400SBM
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX64, CMOS, PBGA208, 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 27 页 / 1197 K
品牌: MERCURY [ MERCURY UNITED ELECTRONICS INC ]
 浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第19页浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第20页浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第21页浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第22页浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第24页浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第25页浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第26页浏览型号W3H32M64EA-400SBM的Datasheet PDF文件第27页  
W3H32M64EA-XSBX  
ADVANCED  
TABLE 12 – AC TIMING PARAMETERS  
-55°C TA +125°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V  
667Mbs CL5  
Symbol  
533Mbs CL4  
400Mbs CL3  
Unit  
Parameter  
Min  
3,000  
3,750  
5,000  
0.48  
Max  
8,000  
8,000  
8,000  
0.52  
Min  
Max  
Min  
Max  
CL=5  
CL=4  
CL=3  
tCK(4)  
CK(4)  
ps  
ps  
ps  
tCK  
tCK  
Clock cycle time  
t
3,750  
5,000  
0.48  
8,000  
8,000  
0.52  
5,000  
5,000  
0.48  
8,000  
8,000  
0.52  
tCK(3)  
tCH  
CK high-level width  
CK low-level width  
tCL  
0.48  
0.52  
0.48  
0.52  
0.48  
0.52  
MIN (tCH  
tCL)  
,
MIN (tCH  
tCL)  
,
MIN (tCH  
tCL)  
,
Half clock period  
tHP  
ps  
DQ output access time from CK/CK#  
Data-out high impedance window from CK/CK#  
Data-out low-impedance window from CK/CK#  
DQ and DM input setup time relative to DQS  
DQ and DM input hold time relative to DQS  
DQ and DM input pulse width (for each input)  
Data hold skew factor  
tAC  
tHZ  
-550  
+650  
-550  
+650  
-600  
+600  
ps  
ps  
ps  
ps  
ps  
tCK  
ps  
ps  
ns  
tCK  
tCK  
ps  
tCK  
tCK  
ps  
tCK  
tCK  
ps  
tCK  
tCK  
tAC(MAX)  
tAC(MAX)  
tAC(MAX)  
tAC(MAX)  
tAC(MAX)  
tAC(MAX)  
tLZ  
tAC(MN)  
400  
tAC(MN)  
400  
tAC(MN)  
450  
tDS  
tDH  
500  
500  
450  
tDIPW  
tQHS  
tQH  
0.35  
0.35  
0.35  
400  
400  
450  
DQ-DQS hold, DQS to rst DQ to go nonvalid, per access  
Data valid output window (DVW)  
tHP - tQHS  
tQH - tDQSQ  
0.35  
0.35  
-550  
0.2  
tHP - tQHS  
tQH - tDQSQ  
0.35  
tHP - tQHS  
tQH - tDQSQ  
0.35  
tDVW  
tDQSH  
tDQSL  
tDQSCK  
tDSS  
DQS input high pulse width  
DQS input low pulse width  
0.35  
0.35  
DQS output access time fromCK/CK#  
DQS falling edge to CK rising - setup time  
DQS falling edge from CK rising - hold time  
O DQS-DQ skew, DOS to last DQ valid, per group, per access  
DQS read preamble  
+650  
-550  
+650  
-600  
+600  
0.2  
0.2  
tDSH  
0.2  
0.2  
0.2  
tDQSQ  
tRPRE  
tRPST  
tWPRES  
tWPRE  
tWPST  
300  
300  
1.1  
0.6  
350  
1.1  
0.6  
0.9  
1.1  
0.6  
0.9  
0.4  
0
0.9  
0.4  
0
DQS read postamble  
0.4  
DQS write preamble setup time  
0
DQS write preamble  
0.25  
0.4  
0.25  
0.4  
0.25  
0.4  
DQS write postamble  
0.6  
0.6  
0.6  
WL-  
TDQSS  
WL+  
TDQSS  
WL-  
TDQSS  
WL+  
TDQSS  
WL-  
TDQSS  
WL+  
TDQSS  
Write command to rst DQS latching transition  
tCK  
tCK  
Positive DQs latch edge to associated edge  
tOQSS  
-0.18  
+0.18  
-0.25  
+0.25  
-0.25  
+0.25  
Microsemi Corporation reserves the right to change products or specications without notice.  
August 2011 © 2011 Microsemi Corporation. All rights reserved.  
Rev.1  
23  
Microsemi Corporation • (602) 437-1520 • www.microsemi.com  
 复制成功!