W3H32M64EA-XSBX
ADVANCED
TABLE 11 – DDR2 ICC SPECIFICATIONS AND CONDITIONS
VCC = 1.8V ±0.1V; -55°C ≤ TA ≤ 125°C
Symbol
667 CL5
533 CL4
400 CL3
Units
Proposed Conditions
Operating one bank active-precharge current;
CK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
ICC0
t
500
600
440
440
mA
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
ICC1
540
520
mA
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDAD6W
Precharge power-down current;
ICC2P
ICC2Q
ICC2N
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
28
28
28
mA
mA
mA
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
220
240
180
200
160
180
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
160
50
120
50
100
50
mA
mA
ICC3P
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC3N
280
1,000
940
240
820
780
200
640
620
mA
mA
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
ICC4W
tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
= tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as IDAD6W
ICC4R
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC5
880
28
840
28
800
28
mA
mA
Self refresh current;
ICC6
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Normal
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK
=
ICC7
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid
1,360
1,360
1,360
mA
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDAD6R
;
Refer to the following page for detailed timing conditions
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev.1
22
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