W3E32M64SA-XB2X
TABLE 2 – CAS LATENCY
READ LATENCY
ALLOWABLE OPERATING FREQUENCY (MHz)
The READ latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the first bit
of output data. The latency can be set to 2 or 2.5 clocks.
SPEED
-200
CAS LATENCY = 2
CAS LATENCY = 2.5
≤ 100
CAS LATENCY = 3
≤ 75
≤ 100
≤ 100
—
—
—
-250
≤ 125
If a READ command is registered at clock edge n, and the latency
is m clocks, the data will be available by clock edge n+m. Table
2 below indicates the operating frequencies at which each CAS
latency setting can be used.
-266
≤ 133
—
-333 (IND)
-333 (MIL)
≤ 166
≤ 166
≤ 166
—
≤ 133
The extended mode register must be loaded when all banks are
idle and no bursts are in progress, and the controller must wait the
specified time before initiating any subsequent operation. Violating
either of these requirements could result in unspecified operation.
Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to zero,
and bits A0-A6 set to the desired values. A DLL reset is initiated
by issuing a MODE REGISTER SET command with bits A7 and
A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to
the desired values. Although not required, JEDEC specifications
recommend when a LOAD MODE REGISTER command is issued
to reset the DLL, it should always be followed by a LOAD MODE
REGISTER command to select normal operating mode.
OUTPUT DRIVE STRENGTH
The normal full drive strength for all outputs are specified to be
SSTL2, Class II. The DDR SDRAM supports an option for reduced
drive. This option is intended for the support of the lighter load and/
or point-to-point environments. The selection of the reduced drive
strength will alter the DQs and DQSs from SSTL2, Class II drive
strength to a reduced drive strength, which is approximately 54
percent of the SSTL2, Class II drive strength.
All other combinations of values forA7-A12 are reserved for future
use and/or test modes. Test modes and reserved states should
not be used because unknown operation or incompatibility with
future versions may result.
DLL ENABLE/DISABLE
When the part is running without the DLL enabled, device
functionality may be altered. The DLL must be enabled for normal
operation. DLLenable is required during power-up initialization and
upon returning to normal operation after having disabled the DLL
for the purpose of debug or evaluation. (When the device exits self
refresh mode, the DLL is enabled automatically.)Any time the DLL
is enabled, 200 clock cycles with CKE high must occur before a
READ command can be issued.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond those
controlled by the mode register; these additional functions are DLL
enable/disable, output drive strength, and QFC. These functions
are controlled via the bits shown in Figure 5. The extended mode
register is programmed via the LOAD MODE REGISTER command
to the mode register (with BA0 = 1 and BA1 = 0) and will retain the
stored information until it is programmed again or the device loses
power. The enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode register (BA0/
BA1 both LOW) to reset the DLL.
Microsemi Corporation reserves the right to change products or specifications without notice.
December 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 1
5
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
