W3E32M64SA-XB2X
FUNCTIONAL DESCRIPTION
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of operation
of the DDR SDRAM. This definition includes the selection of a
burst length, a burst type, a CAS latency, and an operating mode,
as shown in Figure 3. The Mode Register is programmed via the
MODE REGISTER SET command (with BA0 = 0 and BA1 = 0)
and will retain the stored information until it is programmed again
or the device loses power. (Except for bitA8 which is self clearing).
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence.
Accesses begin with the registration of anACTIVE command which
is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command are used to
select the bank and row to be accessed (BA0 and BA1 select the
bank,A0-12 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the starting
column location for the burst access.
Reprogramming the mode register will not alter the contents of
the memory, provided it is performed correctly. The Mode Register
must be loaded (reloaded) when all banks are idle and no bursts
are in progress, and the controller must wait the specified time
before initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Prior to normal operation, the DDR SDRAM must be initialized.
The following sections provide detailed information covering device
initialization, register definition, command descriptions and device
operation.
INITIALIZATION
Mode register bitsA0-A2 specify the burst length,A3 specifies the type
of burst (sequential or interleaved), A4-A6 specify the CAS latency,
and A7-A12 specify the operating mode.
DDR SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified may
result in undefined operation. Power must first be applied to VCC
and VCCQ simultaneously, and then to VREF (and to the system VTT).
BURST LENGTH
V
TT must be applied after VCCQ to avoid device latch-up, which may
Read and write accesses to the DDR SDRAM are burst oriented,
with the burst length being programmable, as shown in Figure
3. The burst length determines the maximum number of column
locations that can be accessed for a given READ or WRITE
command. Burst lengths of 2, 4 or 8 locations are available for
both the sequential and the interleaved burst types.
cause permanent damage to the device. VREF can be applied any
time after VCCQ but is expected to be nominally coincident with
VTT. Except for CKE, inputs are not recognized as valid until after
V
REF is applied. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after VCC is applied.After CKE passes through VIH, it will
transition to an SSTL_2 signal and remain as such until power is
cycled. Maintaining an LVCMOS LOW level on CKE during power-up
is required to ensure that the DQ and DQS outputs will be in the
High-Z state, where they will remain until driven in normal operation
(by a read access). After all power supply and reference voltages
are stable, and the clock is stable, the DDR SDRAM requires a
200μs delay prior to applying an executable command.
Reserved states should not be used, as unknown operation or
incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of columns
equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst will
wrap within the block if a boundary is reached. The block is uniquely
selected by A1-Ai when the burst length is set to two; by A2-Ai
when the burst length is set to four (whereAi is the most significant
column address for a given configuration); and by A3-Ai when
the burst length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to both READ
and WRITE bursts.
Once the 200μs delay has been satisfied, a DESELECT or NOP
command should be applied, and CKE should be brought HIGH.
Following the NOP command, a PRECHARGE ALL command
should be applied. Next a LOAD MODE REGISTER command
should be issued for the extended mode register (BA1 LOW and
BA0 HIGH) to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1 both LOW)
to reset the DLL and to program the operating parameters. Two-
hundred clock cycles are required between the DLL reset and any
READ command. A PRECHARGE ALL command should then be
applied, placing the device in the all banks idle state.
BURST TYPE
Accesses within a given burst may be programmed to be either
sequential or interleaved; this is referred to as the burst type and
is selected via bit M3.
Once in the idle state, two AUTO REFRESH cycles must be
performed (tRFC must be satisfied.) Additionally, a LOAD MODE
REGISTER command for the mode register with the reset DLL
bit deactivated (i.e., to program operating parameters without
resetting the DLL) is required. Following these requirements, the
DDR SDRAM is ready for normal operation.
The ordering of accesses within a burst is determined by the burst
length, the burst type and the starting column address, as shown
in Table 1.
Microsemi Corporation reserves the right to change products or specifications without notice.
December 2014 © 2014 Microsemi Corporation. All rights reserved.
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