欢迎访问ic37.com |
会员登录 免费注册
发布采购

W3E32M64SA-200B2M 参数 Datasheet PDF下载

W3E32M64SA-200B2M图片预览
型号: W3E32M64SA-200B2M
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX64, 0.8ns, CMOS, PBGA219, BGA-219]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 16 页 / 921 K
品牌: MERCURY [ MERCURY UNITED ELECTRONICS INC ]
 浏览型号W3E32M64SA-200B2M的Datasheet PDF文件第4页浏览型号W3E32M64SA-200B2M的Datasheet PDF文件第5页浏览型号W3E32M64SA-200B2M的Datasheet PDF文件第6页浏览型号W3E32M64SA-200B2M的Datasheet PDF文件第7页浏览型号W3E32M64SA-200B2M的Datasheet PDF文件第9页浏览型号W3E32M64SA-200B2M的Datasheet PDF文件第10页浏览型号W3E32M64SA-200B2M的Datasheet PDF文件第11页浏览型号W3E32M64SA-200B2M的Datasheet PDF文件第12页  
W3E32M64SA-XB2X  
FIGURE 4 – CAS LATENCY  
FIGURE 5 – EXTENDED MODE  
REGISTER DEFINITION  
T0  
T1  
T2  
T2n  
T3  
T3n  
CLK#  
CLK  
A8 A7 A6 A5 A4 A3 A2 A1 A0  
BA1 BA0 A12 A11 A10  
A9  
Address Bus  
COMMAND  
READ  
NOP  
NOP  
NOP  
Extended Mode  
Register (Ex)  
1
1
1
CL = 2  
0
DS DLL  
Operating Mode  
DQS  
DQ  
E0  
0
DLL  
Enable  
Disable  
T0  
T1  
T2  
T2n  
T3  
T3n  
1
CLK#  
CLK  
E1  
0
Drive Strength  
Normal  
COMMAND  
READ  
NOP  
NOP  
NOP  
1
Reduced  
CL = 2.5  
DQS  
DQ  
E2  
0
E1, E0  
Valid  
-
Operating Mode  
Reserved  
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3  
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
Burst Length = 4 in the cases shown  
Shown with nominal tAC and nominal tDSDQ  
-
Reserved  
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)  
2. The QFC function is not supported.  
DATA  
DON'T CARE  
TRANSITIONING DATA  
TRUTH TABLE – COMMANDS (NOTE 1)  
NAME (FUNCTION)  
CS#  
H
L
RAS#  
CAS#  
WE#  
X
ADDR  
X
DESELECT (NOP) (9)  
NO OPERATION (NOP) (9)  
X
H
L
X
H
H
L
H
X
ACTIVE (Select bank and activate row) (3)  
L
H
Bank/Row  
Bank/Col  
Bank/Col  
X
READ (Select bank and column, and start READ burst) (4)  
WRITE (Select bank and column, and start WRITE burst) (4)  
BURST TERMINATE (8)  
L
H
H
H
L
H
L
L
L
L
H
H
L
L
PRECHARGE (Deactivate row in bank or banks) ( 5)  
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)  
LOAD MODE REGISTER (2)  
L
L
Code  
X
L
L
H
L
L
L
L
Op-Code  
TRUTH TABLE – DM OPERATION  
NAME (FUNCTION)  
WRITE ENABLE (10)  
WRITE INHIBIT (10)  
DM  
L
DQs  
Valid  
X
H
NOTES:  
1. CKE is HIGH for all commands shown except SELF REFRESH.  
2. A0-12 dene the op-code to be written to the selected Mode Register. BA0, BA1 select either the  
mode register (0, 0) or the extended mode register (1, 0).  
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.  
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for  
CKE.  
3. A0-12 provide row address, and BA0, BA1 provide bank address.  
4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (non persistent),  
while A10 LOW disables the auto precharge feature; BA0, BA1 provide bank address.  
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged  
and BA0, BA1 are “Don’t Care.”  
8. Applies only to read bursts with auto precharge disabled; this command is undened (and  
should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.  
9. DESELECT and NOP are functionally interchangeable.  
10. Used to mask write data; provided coincident with the corresponding data.  
Microsemi Corporation reserves the right to change products or specications without notice.  
December 2014 © 2014 Microsemi Corporation. All rights reserved.  
Rev. 1  
8
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp