W3E32M64SA-XB2X
FIGURE 3 – MODE REGISTER DEFINITION
TABLE 1 – BURST DEFINITION
Order of Accesses Within a Burst
BA1
BA0 A12 A11 A10
A9
A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
Burst
Length
Starting Column
Address
Type = Sequential
Type = Interleaved
Mode Register (Mx)
A0
0*
0*
Operating Mode
CAS Latency BT
Burst Length
2
4
0
1
A0
0
1
0
1
A0
0
1
0
0-1
1-0
0-1
1-0
*
M14 and M13
(BA0 and BA1 must be
"0, 0" to select
the base mode register
(vs. the extended
mode register).
A1
0
0
1
1
A1
0
0
1
1
Burst Length
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
M2 M1 M0
M3 = 0
M3 = 1
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
4
4
8
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A2
0
0
0
0
1
1
1
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
8
1
0
1
0
Burst Type
M3
0
1
Sequential
Interleaved
0
0
1
1
CAS Latency
M6 M5 M4
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column
Reserved
Reserved
Reserved
2.5
within the block.
2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column
within the block.
Reserved
3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting column
within the block.
M11
M12
M10
0
M9
0
M8
0
M7
0
M6-M0
Valid
Operating Mode
4. Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
0
0
Normal Operation
0
0
0
1
0
0
Valid
Normal Operation/Reset DLL
-
-
-
-
-
-
All other states reserved
-
AUTO REFRESH
SELF REFRESH*
AUTO REFRESH is used during normal operation of the DDR
SDRAM and is analogous to CAS-BEFORE-RAS (CBR) REFRESH
in conventional DRAMs. This command is non persistent, so it
must be issued each time a refresh is required.
The SELF REFRESH command can be used to retain data in
the DDR SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the DDR SDRAM retains
data without external clocking. The SELF REFRESH command
is initiated like an AUTO REFRESH command except CKE is
disabled (LOW). The DLL is automatically disabled upon entering
SELF REFRESH and is automatically enabled upon exiting SELF
REFRESH (200 clock cycles must then occur before a READ
command can be issued). Input signals except CKE are “Don’t
Care” during SELF REFRESH. VREF voltage is also required for
the full duration of SELF REFRESH.
The addressing is generated by the internal refresh controller. This
makes the address bits “Don’t Care” during an AUTO REFRESH
command. Each DDR SDRAM requires AUTO REFRESH cycles
at an average interval of tREFI
.
To allow for improved efficiency in scheduling and switching
between tasks, some flexibility in the absolute refresh interval is
provided. A maximum of eight AUTO REFRESH commands can
be posted to any given DDR SDRAM, meaning that the maximum
absolute interval between any AUTO REFRESH command and
the next AUTO REFRESH command is tREFC. This maximum
absolute interval is to allow future support for DLL updates
internal to the DDR SDRAM to be restricted to AUTO REFRESH
cycles, without allowing excessive drift in tAC between updates.
The procedure for exiting self refresh requires a sequence of
commands. First, CK and CK# must be stable prior to CKE going
back HIGH. Once CKE is HIGH, the DDR SDRAM must have
NOP commands issued for tXSNR, because time is required for the
completion of any internal refresh in progress.
Asimple algorithm for meeting both refresh and DLL requirements
is to apply NOPs for tXSNR time, then a DLL Reset and NOPs for
200 additional clock cycles before applying any other command.
* Self refresh available in commercial and industrial temperatures only.
Although not a JEDEC requirement, to provide for future
functionality features, CKE must be active (High) during theAUTO
REFRESH period. The AUTO REFRESH period begins when the
AUTO REFRESH command is registered and ends tRFC later.
Microsemi Corporation reserves the right to change products or specifications without notice.
December 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 1
7
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
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