W3E32M64S-XBX
White Electronic Designs
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(NOTES 1-5, 14-17, 33)
266 Mbs CL 2.5
200 CL 2
250 Mbs CL2.5
200 Mbs CL2
200 Mbs CL2.5
150 Mbs CL2
333 Mbs CL 2.5
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Units
Access window of DQs from CLK/CLK#
tAC
-0.70
0.45
0.45
7.5
+0.70
0.55
0.55
13
-0.75
+0.75
-0.8
+0.8
-0.8
+0.8
ns
CLK high-level width (30)
CLK low-level width (30)
Clock cycle time
tCH
tCL
0.45
0.45
7.5
0.55
0.55
13
0.45
0.45
8
0.55
0.55
13
0.45
0.45
10
0.55
0.55
13
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
μs
μs
ns
ns
tCK
CL = 2.5 (45, 52)
CL = 2 (45, 52)
tCK (2.5)
tCK (2)
tDH
10
13
10
13
10
13
13
15
DQ and DM input hold time relative to DQS (26, 31)
0.45
0.45
1.75
-0.60
0.35
0.35
0.5
0.6
0.6
2
0.6
0.6
2
DQ and DM input setup time relative to DQS (26, 31)
DQ and DM input pulse width (for each input) (31)
Access window of DQS from CLK/CLK#
DQS input high pulse width
tDS
0.5
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
1.75
-0.75
0.35
0.35
+0.60
+0.75
-0.8
0.35
0.35
+0.8
-0.8
0.35
0.35
+0.8
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26)
Write command to first DQS latching transition
DQS falling edge to CLK rising - setup time
DQS falling edge from CLK rising - hold time
Half clock period (34)
0.45
1.25
0.5
0.6
0.6
0.75
0.2
0.75
0.2
1.25
0.75
0.2
1.25
0.75
0.2
1.25
tDSH
0.2
0.2
0.2
0.2
tHP
tCH, tCL
tCH, tCL
tCH, tCL
tCH, tCL
Data-out high-impedance window from CLK/CLK# (18, 42)
Data-out low-impedance window from CLK/CLK# (18, 43)
Address and control input hold time (fast slew rate) (14)
Address and control input setup time (fast slew rate) (14)
Address and control input hold time (slow slew rate) (14)
Address and control input setup time (slow slew rate) (14)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26)
Data hold skew factor
tHZ
+0.70
+0.75
+0.8
+0.8
tLZ
-0.7
0.75
0.75
0.8
-0.75
0.90
0.90
1
-0.8
1.1
1.1
1.1
1.1
16
-0.8
1.1
1.1
1.1
1.1
16
tIH
F
tIS
F
tIH
S
tIS
S
0.8
1
tMRD
tQH
12
15
tHP - tQHS
tHP - tQHS
tHP - tQHS
tHP - tQHS
tQHS
tRAS
tRAP
tRC
0.55
0.75
1
1
ACTIVE to PRECHARGE command (35)
ACTIVE to READ with Auto precharge command (46)
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period (50)
ACTIVE to READ or WRITE delay
42
15
60
72
15
15
0.9
0.4
12
0.25
0
70,000
40
20
65
75
20
20
0.9
0.4
15
0.25
0
120,000
40
20
70
80
20
20
0.9
0.4
15
0.25
0
120,000
40
20
70
80
20
20
0.9
0.4
15
0.25
0
120,000
tRFC
tRCD
tRP
PRECHARGE command period
DQS read preamble (42)
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
1.1
0.6
1.1
0.6
1.1
0.6
1.1
0.6
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time (20, 21)
DQS write postamble (19)
0.4
15
1
0.6
0.4
15
1
0.6
0.4
15
1
0.6
0.4
15
1
0.6
Write recovery time
Internal WRITE to READ command delay
Data valid output window (25)
tWTR
na
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
REFRESH to REFRESH command interval (23)
Average periodic refresh interval (23)
tREFC
tREFI
tVTD
70.3
7.8
70.3
7.8
70.3
7.8
70.3
7.8
Terminating voltage delay to VCC (53)
0
0
0
0
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
tXSNR
tXSRD
75
75
80
80
200
200
200
200
February 2007
Rev. 4
12
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
MERCURY [ MERCURY UNITED ELECTRONICS INC ]
