欢迎访问ic37.com |
会员登录 免费注册
发布采购

MX29LV160CBTC-70G 参数 Datasheet PDF下载

MX29LV160CBTC-70G图片预览
型号: MX29LV160CBTC-70G
PDF下载: 下载PDF文件 查看货源
内容描述: 16M - BIT [ 2Mx8 / 1Mx16 ] CMOS单电压3V仅限于Flash存储器 [16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY]
分类和应用: 闪存存储内存集成电路光电二极管ISM频段
文件页数/大小: 66 页 / 923 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
 浏览型号MX29LV160CBTC-70G的Datasheet PDF文件第13页浏览型号MX29LV160CBTC-70G的Datasheet PDF文件第14页浏览型号MX29LV160CBTC-70G的Datasheet PDF文件第15页浏览型号MX29LV160CBTC-70G的Datasheet PDF文件第16页浏览型号MX29LV160CBTC-70G的Datasheet PDF文件第18页浏览型号MX29LV160CBTC-70G的Datasheet PDF文件第19页浏览型号MX29LV160CBTC-70G的Datasheet PDF文件第20页浏览型号MX29LV160CBTC-70G的Datasheet PDF文件第21页  
MX29LV160C T/B  
Toggle Bit I may be read at any address, and is valid  
after the rising edge of the final WE# or CE#, whichever  
happens first, in the command sequence (prior to the  
program or erase operation), and during the sector time-  
out.  
system may use either OE# or CE# to control the read  
cycles.) But Q2 cannot distinguish whether the sector  
is actively erasing or is erase-suspended. Q6, by com-  
parison, indicates whether the device is actively eras-  
ing, or is in Erase Suspend, but cannot distinguish which  
sectors are selected for erasure. Thus, both status bits  
are required for sectors and mode information. Refer to  
Table 7 to compare outputs for Q2 and Q6.  
During an Automatic Program or Erase algorithm opera-  
tion, successive read cycles to any address cause Q6  
to toggle. The system may use either OE# or CE# to  
control the read cycles.When the operation is complete,  
Q6 stops toggling.  
ReadingToggle Bits Q6/ Q2  
After an erase command sequence is written, if all sec-  
tors selected for erasing are protected, Q6 toggles and  
returns to reading array data. If not all selected sectors  
are protected, the Automatic Erase algorithm erases the  
unprotected sectors, and ignores the selected sectors  
that are protected.  
Whenever the system initially begins reading toggle bit  
status, it must read Q7-Q0 at least twice in a row to  
determine whether a toggle bit is toggling. Typically, the  
system would note and store the value of the toggle bit  
after the first read. After the second read, the system  
would compare the new value of the toggle bit with the  
first. If the toggle bit is not toggling, the device has com-  
pleted the program or erase operation. The system can  
read array data on Q7-Q0 on the following read cycle.  
The system can use Q6 and Q2 together to determine  
whether a sector is actively erasing or is erase sus-  
pended.When the device is actively erasing (that is, the  
Automatic Erase algorithm is in progress), Q6 toggling.  
When the device enters the Erase Suspend mode, Q6  
stops toggling. However, the system must also use Q2  
to determine which sectors are erasing or erase-sus-  
pended. Alternatively, the system can use Q7.  
However, if after the initial two read cycles, the system  
determines that the toggle bit is still toggling, the sys-  
tem also should note whether the value of Q5 is high  
(see the section on Q5). If it is, the system should then  
determine again whether the toggle bit is toggling, since  
the toggle bit may have stopped toggling just as Q5 went  
high. If the toggle bit is no longer toggling, the device  
has successfully completed the program or erase opera-  
tion. If it is still toggling, the device did not complete the  
operation successfully, and the system must write the  
reset command to return to reading array data.  
If a program address falls within a protected sector, Q6  
toggles for approximately 2 us after the program com-  
mand sequence is written, then returns to reading array  
data.  
Q6 also toggles during the erase-suspend-program mode,  
and stops toggling once the Automatic Program algorithm  
is complete.  
The remaining scenario is that system initially determines  
that the toggle bit is toggling and Q5 has not gone high.  
The system may continue to monitor the toggle bit and  
Q5 through successive read cycles, determining the sta-  
tus as described in the previous paragraph. Alternatively,  
it may choose to perform other system tasks. In this  
case, the system must start at the beginning of the al-  
gorithm when it returns to determine the status of the  
operation.  
Table 8 shows the outputs for Toggle Bit I on Q6.  
Q2:Toggle Bit II  
The "Toggle Bit II" on Q2, when used with Q6, indicates  
whether a particular sector is actively erasing (that is,  
the Automatic Erase algorithm is in process), or whether  
that sector is erase-suspended. Toggle Bit II is valid  
after the rising edge of the final WE# or CE#, whichever  
happens first, in the command sequence.  
Q5 : ExceededTiming Limits  
Q5 will indicate if the program or erase time has exceeded  
the specified limits (internal pulse count). Under these  
conditions Q5 will produce a "1". This time-out condition  
indicates that the program or erase cycle was not suc-  
Q2 toggles when the system reads at addresses within  
those sectors that have been selected for erasure. (The  
P/N:PM1186  
REV. 1.2, JAN. 19, 2006  
17  
 复制成功!