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MX29LV160CBTC-70G 参数 Datasheet PDF下载

MX29LV160CBTC-70G图片预览
型号: MX29LV160CBTC-70G
PDF下载: 下载PDF文件 查看货源
内容描述: 16M - BIT [ 2Mx8 / 1Mx16 ] CMOS单电压3V仅限于Flash存储器 [16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY]
分类和应用: 闪存存储内存集成电路光电二极管ISM频段
文件页数/大小: 66 页 / 923 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
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MX29LV160C T/B  
nal reset operation is complete, which requires a time of  
tREADY (during Embedded Algorithms).The system can  
thus monitor RY/BY# to determine whether the reset op-  
eration is complete. If RESET# is asserted when a pro-  
gram or erase operation is completed within a time of  
tREADY (not during Embedded Algorithms).The system  
can read data tRH after the RESET# pin returns toVIH.  
AUTOMATIC CHIP ERASE COMMANDS  
Chip erase is a six-bus cycle operation. There are two  
"unlock" write cycles. These are followed by writing the  
"set-up" command 80H. Two more "unlock" write cycles  
are then followed by the chip erase command 10H.  
The device does not require the system to entirely pre-  
program prior to executing the Automatic Chip Erase.  
Upon executing the Automatic Chip Erase, the device  
will automatically program and verify the entire memory  
for an all-zero data pattern. When the device is auto-  
matically verified to contain an all-zero pattern, a self-  
timed chip erase and verify begin. The erase and verify  
operations are completed when the data on Q7 is "1" at  
which time the device returns to the Read mode. The  
system is not required to provide any control or timing  
during these operations.  
Refer to the AC Characteristics tables for RESET# pa-  
rameters and to Figure 22 for the timing diagram.  
READ/RESET COMMAND  
The read or reset operation is initiated by writing the read/  
reset command sequence into the command register.  
Microprocessor read cycles retrieve array data. The de-  
vice remains enabled for reads until the command regis-  
ter contents are altered.  
When using the Automatic Chip Erase algorithm, note  
that the erase automatically terminates when adequate  
erase margin has been achieved for the memory array  
(no erase verification command is required).  
If program-fail or erase-fail happen, the write of F0H will  
reset the device to abort the operation. A valid com-  
mand must then be written to place the device in the  
desired state.  
If the Erase operation was unsuccessful, the data on Q5  
is "1" (see Table 8), indicating the erase operation ex-  
ceed internal timing limit.  
SILICON-ID READ COMMAND  
Flash memories are intended for use in applications where  
the local CPU alters memory contents. As such, manu-  
facturer and device codes must be accessible while the  
device resides in the target system. PROM program-  
mers typically access signature codes by raising A9 to  
a high voltage (VID). However, multiplexing high voltage  
onto address lines is not generally desired system de-  
sign practice.  
The automatic erase begins on the rising edge of the last  
WE# or CE# pulse, whichever happens first in the com-  
mand sequence and terminates when either the data on  
Q7 is "1" at which time the device returns to the Read  
mode or the data on Q6 stops toggling for two consecu-  
tive read cycles at which time the device returns to the  
Read mode.  
The MX29LV160C T/B contains a Silicon-ID-Read op-  
eration to supple traditional PROM programming meth-  
odology. The operation is initiated by writing the read  
silicon ID command sequence into the command regis-  
ter. Following the command write, a read cycle with  
A1=VIL, A0=VIL retrieves the manufacturer code of C2H/  
00C2H. A read cycle with A1=VIL, A0=VIH returns the  
device code of C4H/22C4H for MX29LV160CT, 49H/2249H  
for MX29LV160CB.  
The system must write the reset command to exit the  
"Silicon-ID Read Command" code.  
P/N:PM1186  
REV. 1.2, JAN. 19, 2006  
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