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MX25L1635DMI-12G 参数 Datasheet PDF下载

MX25L1635DMI-12G图片预览
型号: MX25L1635DMI-12G
PDF下载: 下载PDF文件 查看货源
内容描述: 16M - BIT [ ×1 / ×2 / ×4 ] CMOS串行闪存 [16M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 50 页 / 728 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
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MX25L1635D  
Table 10. AC CHARACTERISTICS (Temperature = -40° C to 85° C for Industrial grade, VCC = 2.7V ~ 3.6V)  
Symbol  
Alt.  
Parameter  
Min.  
Typ. Max.  
Unit  
fSCLK  
fC  
Clock Frequency for the following instructions:  
FAST_READ, PP, SE, BE, CE, DP, RES,RDP  
WREN, WRDI, RDID, RDSR, WRSR  
D.C.  
86 & 104 MHz  
(Condition:15pF)  
D.C.  
66  
MHz  
(Condition:30pF)  
fRSCLK  
fTSCLK  
fR  
fT  
Clock Frequency for READ instructions  
Clock Frequency for 2READ instructions  
Clock Frequency for 4READ instructions  
33  
75  
75  
MHz  
MHz  
MHz  
fQ  
(Condition:15pF)  
ns  
tCH(1)  
tCLH Clock High Time  
tCLL Clock Low Time  
4.8  
4.8  
0.1  
0.1  
5
tCL(1)  
ns  
V/ns  
V/ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
us  
us  
us  
ms  
us  
ms  
ms  
s
tCLCH(2)  
tCHCL(2)  
tSLCH  
tCHSL  
tDVCH  
tCHDX  
tCHSH  
tSHCH  
Clock Rise Time (3) (peak to peak)  
Clock Fall Time (3) (peak to peak)  
tCSS CS# Active Setup Time (relative to SCLK)  
CS# Not Active Hold Time (relative to SCLK)  
tDSU Data In Setup Time  
5
2
tDH  
Data In Hold Time  
5
CS# Active Hold Time (relative to SCLK)  
CS# Not Active Setup Time (relative to SCLK)  
5
5
tSHSL(3) tCSH CS# Deselect Time  
Read  
15  
50  
Write/Erase/Program  
2.7V-3.6V  
tSHQZ(2) tDIS Output Disable Time  
10  
8
3.0V-3.6V  
tCLQV  
tV  
Clock Low to Output Valid  
Loading:30pF/15pF  
2.7V-3.6V  
10/8  
8/6  
3.0V-3.6V  
tCLQX  
tWHSL(4)  
tSHWL(4)  
tDP(2)  
tRES1(2)  
tRES2(2)  
tW  
tHO  
Output Hold Time  
0
Write Protect Setup Time  
Write Protect Hold Time  
CS#HightoDeepPower-downMode  
20  
100  
10  
8.8  
8.8  
100  
300  
5
CS# High to Standby Mode without Electronic Signature Read  
CS# High to Standby Mode with Electronic Signature Read  
Write Status Register Cycle Time  
Byte-Program  
40  
9
tBP  
tPP  
Page Program Cycle Time  
1.4  
60  
0.7  
14  
tSE  
Sector Erase Cycle Time  
300  
2
tBE  
Block Erase Cycle Time  
tCE  
Chip Erase Cycle Time  
30  
s
Notes:  
1. tCH + tCL must be greater than or equal to 1/ fC  
2. Value guaranteed by characterization, not 100% tested in production.  
3. tSHSL=15ns from read instruction, tSHSL=50ns from Write/Erase/Program instruction.  
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.  
5. Test condition is shown as Figure 4, 5.  
P/N:PM1374  
REV. 1.5, OCT. 01, 2008  
29  
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