MX25L12845E
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
(19) Continuously program mode (CP mode)
The CP mode may enhance program performance by automatically increasing address to the next higher address
after each byte data has been programmed.
The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction
must execute to set the Write Enable Latch(WEL) bit before sending the Continuously program (CP) instruction.
CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of
data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address
range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If
more than two bytes data are input, the additional data will be ignored and only two byte data are valid. Any byte to
be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unpro-
tected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP
mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction.
During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05
hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cy-
cle, which means the WIP bit=0.
The sequence of issuing CP instruction is : CS# high to low → sending CP instruction code → 3-byte address on SI
pin -> two data bytes on SI → CS# goes high to low → sending CP instruction and then continue two data bytes are
programmed → CS# goes high to low -> till last desired two data bytes are programmed → CS# goes high to low
→sending WRDI (Write Disable) instruction to end CP mode → send RDSR instruction to verify if CP mode word
program ends, or send RDSCUR to check bit4 to verify if CP mode ends. (see Figure 28 of CP mode timing wave-
form)
Three methods to detect the completion of a program cycle during CP mode:
1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.
2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not.
3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a
program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is
enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indi-
cates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to
disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the
ESRY/DSRY command are not accepted unless the completion of CP mode.
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
(20) Parallel Mode (Highly recommended for production throughputs increasing)
The parallel mode provides 8 bit inputs/outputs for increasing throughputs of factory production purpose. The
parallel mode requires 55h command code, after writing the parallel mode command and then CS# going high, after
that, the Memory can be available to accept read/program/read status/read ID/RES/REMS command as the normal
writing command procedure.
a. Only effective for Read Array for normal read(not FAST_READ), Read ID, Page Program, RES and REMS write
data period.
b. For normal write command (by SI), No effect
c. Under parallel mode, the fastest access clock freq. will be changed to 6MHz(SCLK pin clock freq.)
d. For parallel mode, the tV will be changed to 70ns.
P/N: PM1428
REV. 0.06, MAR. 05, 2009
26
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