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MX25L12845EMI-10G 参数 Datasheet PDF下载

MX25L12845EMI-10G图片预览
型号: MX25L12845EMI-10G
PDF下载: 下载PDF文件 查看货源
内容描述: 128M - BIT [ ×1 / ×2 / ×4 ] CMOS MXSMIO (串行多I / O )Flash存储器 [128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY]
分类和应用: 存储
文件页数/大小: 69 页 / 3278 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
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MX25L12845E  
Table 8. ID Definitions  
manufacturer ID  
C2  
memory type  
memory density  
18  
RDID Command  
20  
electronic ID  
17  
RES Command  
manufacturer ID  
C2  
device ID  
17  
REMS/REMS2/REMS4/  
REMS4D Command  
(24) Enter Secured OTP (ENSO)  
The ENSO instruction is for entering the additional 4K-bit Secured OTP mode. The additional 4K-bit Secured OTP  
is independent from main array, which may use to store unique serial number for system identifier. After entering  
the Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data.  
The Secured OTP data cannot be updated again once it is lock-down.  
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP  
mode → CS# goes high.  
Please note that WRSR/WRSCUR/WPSEL/SBLK/GBLK/SBULK/GBULK/CE/BE/SE/BE32K commands are not ac-  
ceptable during the access of secure OTP region, once Security OTP is lock down, only read related commands  
are valid.  
(25) Exit Secured OTP (EXSO)  
The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode.  
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP  
mode→ CS# goes high.  
(26) Read Security Register (RDSCUR)  
The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read at  
any time (even in program/erase/write status register/write security register condition) and continuously.  
The sequence of issuing RDSCUR instruction is : CS# goes low→ send ing RDSCUR instruction → Security Regis-  
ter data out on SO→ CS# goes high.  
The definition of the Security Register is as below:  
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory  
or not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock.  
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus-  
tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP  
area cannot be update any more. While it is in 4K-bit Secured OTP mode, array access is not allowed.  
P/N: PM1428  
REV. 0.06, MAR. 05, 2009  
28